From owner-freebsd-bugs Tue Dec 31 11:30:05 1996 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.4/8.8.4) id LAA15733 for bugs-outgoing; Tue, 31 Dec 1996 11:30:05 -0800 (PST) Received: (from gnats@localhost) by freefall.freebsd.org (8.8.4/8.8.4) id LAA15718; Tue, 31 Dec 1996 11:30:02 -0800 (PST) Date: Tue, 31 Dec 1996 11:30:02 -0800 (PST) Message-Id: <199612311930.LAA15718@freefall.freebsd.org> To: freebsd-bugs Cc: From: George Simunovich Subject: Re: kern/2270: Hayes ESP serial card locks system as of 12/01 ke Reply-To: George Simunovich Sender: owner-bugs@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk The following reply was made to PR kern/2270; it has been noted by GNATS. From: George Simunovich To: Bruce Evans Cc: freebsd-gnats-submit@freebsd.org Subject: Re: kern/2270: Hayes ESP serial card locks system as of 12/01 ke Date: Tue, 31 Dec 1996 11:58:07 -0700 (MST) Ok, here is new "development". I recompiled a kernel, without any changes to the code, and included the kernel debugger, "DDB". I then booted the new kernel with the switches "-sd". I think I'll show you what I did... db>break siostop db>c #cat > /dev/cuaa2 ^D db>c db>c db>c # It doesn't lock up. I can do this over and over again without any problems. Unfortunatly, going back into the debugger and deleteing the breakpoint at siostop and trying the cat again, it completely locks up again. I'm very confused. On 28-Dec-96 Bruce Evans wrote: >Look at the magic outb for the ESP case near line 902. This sets the >FIFO_RCV_RST and FIFO_XMT_RST bits in combination with the FIFO_DMA_MODE >bit. I don't know what this does (I don't have any documentation about >the ESP). The author of the ESP changes said that the DMA bit doesn't >have anything to do with DMA. Apparently the reset bits aren't for reset >either. While looking through the ESP information I found at ftp.hayes.com I found this: Operating in UART Compatibility Mode at 115,200 or 230,400 Bit/s ------------------------------------------------------------ To operate in UART Compatibility Mode at 115,200 or 230,400 bit/s, follow these steps: Step 1: Determine if any of the COM1 through COM4 ports is an ESP Communications Accelerator Version 2.0 port. This can be done by searching through the valid M aster/Slave I/O addresses as follows: * Read the Base I/O address and look for the signature 0F3h. If the value is found, issue the Get Self Test Results (01h) command and mask off all bits except for bits 4, 5, and 6 (the hardware type bits). The first version of the COM-bic chip will have a value of 010. * Issue the Get Compatibility Mode DIP Switch (02h) command. Bits 0 and 1 to identify the COM designation. Step 2: Repeat the above steps for all master I/O addresses and any slaves that are associated with a found master. Step 3: Do the 'normal' 16550 initialization. Step 4: Enable the FIFOs at the UART FIFO Control Register, FCR, bit 0. Note: Due to a problem with the receive trigger level enable in UART mode the DM A mode select bit (bit 3) should also be set when enabling the FIFO's. Step 5: Scale the UART trigger levels using the Set Mode (10h) command CMD2, bit 7. You can significantly reduce the number of interrupts by scaling the trigger levels to 1, 64, 256, and 512 bytes. While issuing the Set Mode command, CMD2 b it 1 should be set to ensure that the Compatibility Mode UART FIFOs are enabled. Step 6: Issue the Set Flow Control Type (08h) command for the type of flow contr ol desired. Step 7: Issue the Set Rx Flow Control (0Ah) command to set the flow control leve ls. Step 8: For Hardware Flow Control, set the appropriate bits (0 and 1) in the UAR T Modem Control Register (MCR) to turn on RTS and DTR. Step 9: Set the bit/s rate. If 230,400 bit/s is desired, set the bit/s to 115,20 0 and issue the Set UART Clock ESI Prescaler (23h) command with a value of 01. Step 10: The interrupt service routine should probably be altered to take advant age of transmit and receive buffers that are 1KB each. Note: For software flow control, there are two ESI commands available that flow on and off the local transmitter. The note for Step 4 is interresting and explains setting the DMA bit for the magic outb??? Back to my random changes to sio.c.... George ------------------------------------ George Simunovich