From owner-svn-src-all@freebsd.org Tue Sep 6 19:29:16 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8B12BBC62A0; Tue, 6 Sep 2016 19:29:16 +0000 (UTC) (envelope-from davidcs@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 56949664; Tue, 6 Sep 2016 19:29:16 +0000 (UTC) (envelope-from davidcs@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u86JTF5C088434; Tue, 6 Sep 2016 19:29:15 GMT (envelope-from davidcs@FreeBSD.org) Received: (from davidcs@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u86JTEx1088428; Tue, 6 Sep 2016 19:29:14 GMT (envelope-from davidcs@FreeBSD.org) Message-Id: <201609061929.u86JTEx1088428@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: davidcs set sender to davidcs@FreeBSD.org using -f From: David C Somayajulu Date: Tue, 6 Sep 2016 19:29:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r305491 - stable/10/sys/dev/qlxgbe X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2016 19:29:16 -0000 Author: davidcs Date: Tue Sep 6 19:29:14 2016 New Revision: 305491 URL: https://svnweb.freebsd.org/changeset/base/305491 Log: MFC 304249 Add support for set/get cam search mode Modified: stable/10/sys/dev/qlxgbe/ql_dbg.h stable/10/sys/dev/qlxgbe/ql_hw.c stable/10/sys/dev/qlxgbe/ql_hw.h stable/10/sys/dev/qlxgbe/ql_isr.c stable/10/sys/dev/qlxgbe/ql_os.c stable/10/sys/dev/qlxgbe/ql_ver.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/qlxgbe/ql_dbg.h ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_dbg.h Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_dbg.h Tue Sep 6 19:29:14 2016 (r305491) @@ -52,6 +52,7 @@ extern void ql_dump_buf32(qla_host_t *ha #define INJCT_MBX_CMD_FAILURE 0x00008 #define INJCT_HEARTBEAT_FAILURE 0x00009 #define INJCT_TEMPERATURE_FAILURE 0x0000A +#define INJCT_M_GETCL_M_GETJCL_FAILURE 0x0000B #ifdef QL_DBG Modified: stable/10/sys/dev/qlxgbe/ql_hw.c ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_hw.c Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_hw.c Tue Sep 6 19:29:14 2016 (r305491) @@ -74,6 +74,8 @@ static int qla_query_fw_dcbx_caps(qla_ho static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits); static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits); static void qla_get_quick_stats(qla_host_t *ha); +static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode); +static int qla_get_cam_search_mode(qla_host_t *ha); static void ql_minidump_free(qla_host_t *ha); @@ -94,11 +96,22 @@ qla_sysctl_get_drvr_stats(SYSCTL_HANDLER ha = (qla_host_t *)arg1; - for (i = 0; i < ha->hw.num_sds_rings; i++) + for (i = 0; i < ha->hw.num_sds_rings; i++) { + device_printf(ha->pci_dev, "%s: sds_ring[%d] = %p\n", __func__,i, (void *)ha->hw.sds[i].intr_count); + device_printf(ha->pci_dev, + "%s: sds_ring[%d].spurious_intr_count = %p\n", + __func__, + i, (void *)ha->hw.sds[i].spurious_intr_count); + + device_printf(ha->pci_dev, + "%s: sds_ring[%d].rx_free = %d\n", __func__,i, + ha->hw.sds[i].rx_free); + } + for (i = 0; i < ha->hw.num_tx_rings; i++) device_printf(ha->pci_dev, "%s: tx[%d] = %p\n", __func__,i, @@ -255,6 +268,47 @@ qla_sysctl_set_port_cfg_exit: return err; } +static int +qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS) +{ + int err, ret = 0; + qla_host_t *ha; + + err = sysctl_handle_int(oidp, &ret, 0, req); + + if (err || !req->newptr) + return (err); + + ha = (qla_host_t *)arg1; + + if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) || + (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) { + err = qla_set_cam_search_mode(ha, (uint32_t)ret); + } else { + device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret); + } + + return (err); +} + +static int +qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS) +{ + int err, ret = 0; + qla_host_t *ha; + + err = sysctl_handle_int(oidp, &ret, 0, req); + + if (err || !req->newptr) + return (err); + + ha = (qla_host_t *)arg1; + err = qla_get_cam_search_mode(ha); + + return (err); +} + + /* * Name: ql_hw_add_sysctls * Function: Add P3Plus specific sysctls @@ -362,6 +416,24 @@ ql_hw_add_sysctls(qla_host_t *ha) " 1 = xmt only; 2 = rcv only;\n" ); + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), + OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, + (void *)ha, 0, + qla_sysctl_set_cam_search_mode, "I", + "Set CAM Search Mode" + "\t 1 = search mode internal\n" + "\t 2 = search mode auto\n"); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), + OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, + (void *)ha, 0, + qla_sysctl_get_cam_search_mode, "I", + "Get CAM Search Mode" + "\t 1 = search mode internal\n" + "\t 2 = search mode auto\n"); + ha->hw.enable_9kb = 1; SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), @@ -407,7 +479,8 @@ ql_hw_add_sysctls(qla_host_t *ha) "\t\t\t 7: ocm: offchip memory rd_wr failure\n" "\t\t\t 8: mbx: mailbox command failure\n" "\t\t\t 9: heartbeat failure\n" - "\t\t\t A: temperature failure\n" ); + "\t\t\t A: temperature failure\n" + "\t\t\t 11: m_getcl or m_getjcl failure\n" ); SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), @@ -1299,6 +1372,85 @@ qla_config_fw_lro(qla_host_t *ha, uint16 return 0; } +static int +qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode) +{ + device_t dev; + q80_hw_config_t *hw_config; + q80_hw_config_rsp_t *hw_config_rsp; + uint32_t err; + + dev = ha->pci_dev; + + hw_config = (q80_hw_config_t *)ha->hw.mbox; + bzero(hw_config, sizeof (q80_hw_config_t)); + + hw_config->opcode = Q8_MBX_HW_CONFIG; + hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT; + hw_config->count_version |= Q8_MBX_CMD_VERSION; + + hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE; + + hw_config->u.set_cam_search_mode.mode = search_mode; + + if (qla_mbx_cmd(ha, (uint32_t *)hw_config, + (sizeof (q80_hw_config_t) >> 2), + ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { + device_printf(dev, "%s: failed\n", __func__); + return -1; + } + hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; + + err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); + + if (err) { + device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); + } + + return 0; +} + +static int +qla_get_cam_search_mode(qla_host_t *ha) +{ + device_t dev; + q80_hw_config_t *hw_config; + q80_hw_config_rsp_t *hw_config_rsp; + uint32_t err; + + dev = ha->pci_dev; + + hw_config = (q80_hw_config_t *)ha->hw.mbox; + bzero(hw_config, sizeof (q80_hw_config_t)); + + hw_config->opcode = Q8_MBX_HW_CONFIG; + hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT; + hw_config->count_version |= Q8_MBX_CMD_VERSION; + + hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE; + + if (qla_mbx_cmd(ha, (uint32_t *)hw_config, + (sizeof (q80_hw_config_t) >> 2), + ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { + device_printf(dev, "%s: failed\n", __func__); + return -1; + } + hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; + + err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); + + if (err) { + device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); + } else { + device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__, + hw_config_rsp->u.get_cam_search_mode.mode); + } + + return 0; +} + + + static void qla_xmt_stats(qla_host_t *ha, q80_xmt_stats_t *xstat, int i) { Modified: stable/10/sys/dev/qlxgbe/ql_hw.h ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_hw.h Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_hw.h Tue Sep 6 19:29:14 2016 (r305491) @@ -255,6 +255,7 @@ #define Q8_MBX_LINK_EVENT_REQ 0x0048 #define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 #define Q8_MBX_CONFIG_FW_LRO 0x004A +#define Q8_MBX_HW_CONFIG 0x004C #define Q8_MBX_INIT_NIC_FUNC 0x0060 #define Q8_MBX_STOP_NIC_FUNC 0x0061 #define Q8_MBX_IDC_REQ 0x0062 @@ -622,6 +623,87 @@ typedef struct _q80_config_md_templ_cmd_ } __packed q80_config_md_templ_cmd_rsp_t; /* + * Hardware Configuration Commands + */ + +typedef struct _q80_hw_config { + uint16_t opcode; + uint16_t count_version; +#define Q8_HW_CONFIG_SET_MDIO_REG_COUNT 0x06 +#define Q8_HW_CONFIG_GET_MDIO_REG_COUNT 0x05 +#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03 +#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02 +#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT 0x03 +#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT 0x02 +#define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT 0x02 + + uint32_t cmd; +#define Q8_HW_CONFIG_SET_MDIO_REG 0x01 +#define Q8_HW_CONFIG_GET_MDIO_REG 0x02 +#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE 0x03 +#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE 0x04 +#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD 0x07 +#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD 0x08 +#define Q8_HW_CONFIG_GET_ECC_COUNTS 0x0A + + union { + struct { + uint32_t phys_port_number; + uint32_t phy_dev_addr; + uint32_t reg_addr; + uint32_t data; + } set_mdio; + + struct { + uint32_t phys_port_number; + uint32_t phy_dev_addr; + uint32_t reg_addr; + } get_mdio; + + struct { + uint32_t mode; +#define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL 0x1 +#define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO 0x2 + + } set_cam_search_mode; + + struct { + uint32_t value; + } set_temp_threshold; + } u; +} __packed q80_hw_config_t; + +typedef struct _q80_hw_config_rsp { + uint16_t opcode; + uint16_t regcnt_status; + + union { + struct { + uint32_t value; + } get_mdio; + + struct { + uint32_t mode; + } get_cam_search_mode; + + struct { + uint32_t temp_warn; + uint32_t curr_temp; + uint32_t osc_ring_rate; + uint32_t core_voltage; + } get_temp_threshold; + + struct { + uint32_t ddr_ecc_error_count; + uint32_t ocm_ecc_error_count; + uint32_t l2_dcache_ecc_error_count; + uint32_t l2_icache_ecc_error_count; + uint32_t eport_ecc_error_count; + } get_ecc_counts; + } u; +} __packed q80_hw_config_rsp_t; + +/* * Link Event Request Command */ typedef struct _q80_link_event { @@ -1407,6 +1489,7 @@ typedef struct _qla_sds { volatile uint32_t rcv_active; uint32_t sds_consumer; uint64_t intr_count; + uint64_t spurious_intr_count; } qla_sds_t; #define Q8_MAX_LRO_CONT_DESC 7 Modified: stable/10/sys/dev/qlxgbe/ql_isr.c ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_isr.c Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_isr.c Tue Sep 6 19:29:14 2016 (r305491) @@ -464,6 +464,8 @@ qla_rcv_isr(qla_host_t *ha, uint32_t sds qla_sgl_comp_t sgc; uint16_t nhandles; uint32_t sds_replenish_threshold = 0; + uint32_t r_idx = 0; + qla_sds_t *sdsp; dev = ha->pci_dev; hw = &ha->hw; @@ -706,8 +708,18 @@ qla_rcv_isr(qla_host_t *ha, uint32_t sds if (hw->sds[sds_idx].sdsr_next != comp_idx) { QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx); + hw->sds[sds_idx].sdsr_next = comp_idx; + } else { + hw->sds[sds_idx].spurious_intr_count++; + + if (ha->hw.num_rds_rings > 1) + r_idx = sds_idx; + + sdsp = &ha->hw.sds[sds_idx]; + + if (sdsp->rx_free > ha->std_replenish) + qla_replenish_normal_rx(ha, sdsp, r_idx); } - hw->sds[sds_idx].sdsr_next = comp_idx; sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx]; opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1])); @@ -827,6 +839,20 @@ ql_mbx_isr(void *arg) device_printf(ha->pci_dev, "%s: sfp removed]\n", __func__); break; + case 0x8140: + { + uint32_t ombx[3]; + + ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); + ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); + ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); + + device_printf(ha->pci_dev, "%s: " + "0x%08x 0x%08x 0x%08x 0x%08x \n", + __func__, data, ombx[0], ombx[1], ombx[2]); + } + break; + default: device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data); break; @@ -873,8 +899,8 @@ qla_replenish_normal_rx(qla_host_t *ha, rdesc->rx_next = 0; } else { device_printf(ha->pci_dev, - "%s: ql_get_mbuf [0,(%d),(%d)] failed\n", - __func__, rdesc->rx_in, rxb->handle); + "%s: qla_get_mbuf [(%d),(%d),(%d)] failed\n", + __func__, r_idx, rdesc->rx_in, rxb->handle); rxb->m_head = NULL; rxb->next = sdsp->rxb_free; Modified: stable/10/sys/dev/qlxgbe/ql_os.c ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_os.c Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_os.c Tue Sep 6 19:29:14 2016 (r305491) @@ -1597,6 +1597,9 @@ ql_get_mbuf(qla_host_t *ha, qla_rx_buf_t if (mp == NULL) { + if (QL_ERR_INJECT(ha, INJCT_M_GETCL_M_GETJCL_FAILURE)) + return(-1); + if (ha->hw.enable_9kb) mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, mbuf_size); else Modified: stable/10/sys/dev/qlxgbe/ql_ver.h ============================================================================== --- stable/10/sys/dev/qlxgbe/ql_ver.h Tue Sep 6 19:27:00 2016 (r305490) +++ stable/10/sys/dev/qlxgbe/ql_ver.h Tue Sep 6 19:29:14 2016 (r305491) @@ -36,6 +36,6 @@ #define QLA_VERSION_MAJOR 3 #define QLA_VERSION_MINOR 10 -#define QLA_VERSION_BUILD 29 +#define QLA_VERSION_BUILD 30 #endif /* #ifndef _QL_VER_H_ */