From owner-freebsd-current@FreeBSD.ORG Wed Jun 16 16:25:31 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id D82ED16A4CE for ; Wed, 16 Jun 2004 16:25:31 +0000 (GMT) Received: from mail.spekt.net (biggie.spekt.net [67.18.79.74]) by mx1.FreeBSD.org (Postfix) with ESMTP id 9858443D39 for ; Wed, 16 Jun 2004 16:25:31 +0000 (GMT) (envelope-from radek@raadradd.com) Received: by mail.spekt.net (Postfix, from userid 1003) id B666A400C; Wed, 16 Jun 2004 18:24:34 +0200 (CEST) Received: from [172.16.106.231] (unknown [212.130.239.102]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.spekt.net (Postfix) with ESMTP id DCD2C3FDB; Wed, 16 Jun 2004 18:24:33 +0200 (CEST) Message-ID: <40D07430.1070504@raadradd.com> Date: Wed, 16 Jun 2004 18:24:16 +0200 From: Radek Kozlowski User-Agent: Mozilla Thunderbird 0.6 (X11/20040601) X-Accept-Language: en-us, en MIME-Version: 1.0 To: John Polstra References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit cc: Alexander Leidinger cc: current@freebsd.org Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2004 16:25:32 -0000 On 2004.06.16 18:11, John Polstra wrote: > On 16-Jun-2004 Alexander Leidinger wrote: > >>Hi, >> >>I'm working with Alan and Chad David on automatic tuning of the number >>of colors for the page queue. For AMD CPUs (including amd64, but not >>tested) we already have code in identcpu.c to determine the size of the >>L2 cache and its associativity. >> >>Now I need to know how to determine those properties on at least some >>Intel CPUs (e.g. P3 & P4). >> >>Since Intel has a lot of manuals and everyone contains a lot of pages, I >>decided to first ask here if someone can give me a pointer please (or >>working code). > > > Check out the "misc/cpuid" port. Here's some sample output from a > PIII system. Cache information is at the end. > The latest version of cpuid is from 2002 and at least for my Athlon XP-M processor it doesn't read the information about L2 cache correctly. IIRC, for my L2 size it only takes one byte from the beginning of ecx register, whereas in my case it is stored in two, a.s.o. So I wouldn't rely on cpuid when it comes to newer CPUs. -Radek