Date: Fri, 14 Jul 2006 16:37:18 GMT From: Oleksandr Tymoshenko <gonzo@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 101571 for review Message-ID: <200607141637.k6EGbIkS006300@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=101571 Change 101571 by gonzo@gonzo_hq on 2006/07/14 16:36:42 o Intergarted @101401, @101410. o Hardocded TLB/memory values for gxemul/malta "device". o stole cpu_thread_setup from juli's code. o Add panic() string to stub functions in vm_panic.c. Makes life easier, a lot. Affected files ... .. //depot/projects/mips2/src/sys/mips/include/cache.h#2 integrate .. //depot/projects/mips2/src/sys/mips/include/pte.h#2 integrate .. //depot/projects/mips2/src/sys/mips/include/tlb.h#3 integrate .. //depot/projects/mips2/src/sys/mips/include/vmparam.h#5 integrate .. //depot/projects/mips2/src/sys/mips/mips/cpu.c#9 edit .. //depot/projects/mips2/src/sys/mips/mips/exception.S#3 integrate .. //depot/projects/mips2/src/sys/mips/mips/machdep.c#15 edit .. //depot/projects/mips2/src/sys/mips/mips/pmap.c#5 integrate .. //depot/projects/mips2/src/sys/mips/mips/support.S#5 edit .. //depot/projects/mips2/src/sys/mips/mips/tlb.c#6 integrate .. //depot/projects/mips2/src/sys/mips/mips/vm_machdep.c#3 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/include/cache.h#2 (text+ko) ==== @@ -204,6 +204,10 @@ (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \ } while (/*CONSTCOND*/0) +/* + * XXXMIPS: remove this calles while mipc cache ops are not defined + */ +#ifdef notyet #define mips_icache_sync_all() \ (*mips_cache_ops.mco_icache_sync_all)() @@ -227,6 +231,18 @@ #define mips_dcache_wb_range(v, s) \ __mco_2args(, dcache_wb_range, (v), (s)) +#else +#define mips_icache_sync_all() +#define mips_icache_sync_range(v, s) +#define mips_icache_sync_range_index(v, s) +#define mips_dcache_wbinv_all() +#define mips_dcache_wbinv_range(v, s) +#define mips_dcache_wbinv_range_index(v, s) +#define mips_dcache_inv_range(v, s) +#define mips_dcache_wb_range(v, s) +#endif + + void mips_config_cache(void); void mips_dcache_compute_align(void); ==== //depot/projects/mips2/src/sys/mips/include/pte.h#2 (text+ko) ==== @@ -1,4 +1,5 @@ /*- + * Copyright (c) 2006 Oleksandr Tymoshenko <gonzo@freebsd.org> * Copyright (c) 2003-2004 Juli Mallett <jmallett@FreeBSD.org> * All rights reserved. * @@ -23,14 +24,14 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $P4: //depot/projects/mips2/src/sys/mips/include/pte.h#1 $ + * $P4: //depot/projects/mips2/src/sys/mips/include/pte.h#2 $ */ #ifndef _MACHINE_PTE_H_ #define _MACHINE_PTE_H_ /* - * 64-bit PTE. + * 32-bit PTE. */ #ifndef LOCORE typedef unsigned long pt_entry_t; @@ -44,55 +45,31 @@ /* * PFN for EntryLo register. Upper bits are 0, which is to say that - * bit 29 is the last hardware bit; Bits 30 and upwards (EntryLo is - * 64 bit though it can be referred to in 32-bits providing 2 software - * bits safely. We use it as 64 bits to get many software bits, and - * god knows what else.) are unacknowledged by hardware. They may be - * written as anything, but otherwise they have as much meaning as - * other 0 fields. + * bit 29 is the last hardware bit; Bits 30 and upwards are + * unacknowledged by hardware. They may be written as anything, but + * otherwise they have as much meaning as other 0 fields. * * Given this, we just shift the PA right a little. */ #define MIPS_TLB_SWSHIFT 30 #define MIPS_PFN_SHIFT 6 -#define MIPS_PFN_MASK 0x3FFFFFC0 +#define MIPS_PFN_MASK 0xFFFFFF #define MIPS_PA_TO_PFN(pa) (((pa) >> MIPS_PFN_SHIFT) & MIPS_PFN_MASK) #define MIPS_PFN_TO_PA(pfn) ((pfn) << MIPS_PFN_SHIFT) #define MIPS_PTE_TO_PFN(pte) ((pte) & MIPS_PFN_MASK) #define MIPS_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS_PTE_TO_PFN((pte)))) /* - * VPN for EntryHi register. Upper two bits select user, supervisor, - * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to - * as low as 13, down to PAGE_SHIFT + 1, to index 2 pages. From bit 12 - * to bit 8 there is a 5-bit 0 field. Low byte is ASID. + * VPN for EntryHi register. Upper upper 19 bits are VPN2 - VA[31..13] + * or PFN/2. EntryHi[12..11] - VPN2X field for Release 2 architecture + * to support 1Kb pages. Bits 10..8 shoud be set to zero. Bits 7..0 - + * contains ASID. VPN2X bits should be set to zero in Release 1. + * XXX: add support for VPN2X(?) */ -#define MIPS_HI_R_SHIFT 62 -#ifdef LOCORE -#define MIPS_HI_R_USER (0x00 << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_SUPERVISOR (0x01 << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_KERNEL (0x03 << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_MASK (0x03 << MIPS_HI_R_SHIFT) -#else -#define MIPS_HI_R_USER (0x00UL << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_SUPERVISOR (0x01UL << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_KERNEL (0x03UL << MIPS_HI_R_SHIFT) -#define MIPS_HI_R_MASK (0x03UL << MIPS_HI_R_SHIFT) -#endif -#define MIPS_HI_VA_R(va) ((va) & MIPS_HI_R_MASK) -#define MIPS_HI_FILL_SHIFT 40 -#define MIPS_HI_FILL_MASK ((0x7FFFFFUL) << MIPS_HI_FILL_SHIFT) -#define MIPS_HI_VA_FILL(va) ((((va) & (1UL << 63)) != 0 ? MIPS_HI_FILL_MASK : 0)) #define MIPS_HI_VPN2_SHIFT (PAGE_SHIFT + 1) -#ifdef LOCORE -#define MIPS_HI_VPN2_MASK (((~((1 << MIPS_HI_VPN2_SHIFT) - 1)) << (63 - MIPS_HI_FILL_SHIFT)) >> (63 - MIPS_HI_FILL_SHIFT)) -#else -#define MIPS_HI_VPN2_MASK (((~((1UL << MIPS_HI_VPN2_SHIFT) - 1)) << (63 - MIPS_HI_FILL_SHIFT)) >> (63 - MIPS_HI_FILL_SHIFT)) -#endif +#define MIPS_HI_VPN2_MASK (0xffffffff << MIPS_HI_VPN2_SHIFT) #define MIPS_HI_VA_TO_VPN2(va) ((va) & MIPS_HI_VPN2_MASK) -#define MIPS_HI_ENTRY(va, asid) ((MIPS_HI_VA_R((va))) /* Region. */ | \ - (MIPS_HI_VA_FILL((va))) /* Fill. */ | \ - (MIPS_HI_VA_TO_VPN2((va))) /* VPN2. */ | \ +#define MIPS_HI_ENTRY(va, asid) ((MIPS_HI_VA_TO_VPN2((va))) /* VPN2. */ | \ ((asid))) /* @@ -108,10 +85,7 @@ */ #define PG_C(attr) ((attr & 0x07) << 3) #define PG_C_UNCACHED (PG_C(0x02)) -#define PG_C_CNC (PG_C(0x03)) -#define PG_C_CCE (PG_C(0x04)) -#define PG_C_CCEOW (PG_C(0x05)) -#define PG_C_CCUOW (PG_C(0x06)) +#define PG_C_CACHED (PG_C(0x03)) #define PG_D 0x04 #define PG_V 0x02 #define PG_G 0x01 ==== //depot/projects/mips2/src/sys/mips/include/tlb.h#3 (text+ko) ==== @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $P4: //depot/projects/mips2/src/sys/mips/include/tlb.h#2 $ + * $P4: //depot/projects/mips2/src/sys/mips/include/tlb.h#3 $ */ #ifndef _MACHINE_TLB_H_ @@ -32,7 +32,7 @@ extern pt_entry_t *kptmap; extern vm_size_t kptsize; -#define tlb_pte_index(va) (((va) - (MIPS_KSEG2_START)) >> PAGE_SHIFT) +#define tlb_pte_index(va) (((va) - (VM_MIN_KERNEL_ADDRESS)) >> PAGE_SHIFT) #define tlb_pte_find(t,va) (&(t)[tlb_pte_index((va))]) void tlb_bootstrap(vm_size_t, vm_offset_t (*)(vm_size_t)); ==== //depot/projects/mips2/src/sys/mips/include/vmparam.h#5 (text+ko) ==== @@ -99,11 +99,15 @@ #ifndef VM_INITIAL_PAGEIN #define VM_INITIAL_PAGEIN 16 #endif -#define VM_MIN_ADDRESS ((vm_offset_t)0x0000000000001000) + +/* + * XXXMIPS: This values need to be changed!!! + */ +#define VM_MIN_ADDRESS ((vm_offset_t)0x0000000000010000) #define VM_MAXUSER_ADDRESS ((vm_offset_t)0x0000000100000000) #define VM_MAX_ADDRESS ((vm_offset_t)0x0000000100000000) -#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)MIPS_KSEG0_START) -#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)MIPS_KSEG1_START-1) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0x0000000000010000) +#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)MIPS_KSEG0_START-1) #define KERNBASE (VM_MIN_KERNEL_ADDRESS) /* virtual sizes (bytes) for various kernel submaps */ ==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#9 (text+ko) ==== @@ -125,7 +125,7 @@ { VECI(MIPS_UTLB_MISS, TLBMiss); - VECI(MIPS3_XTLB_MISS, XTLBMiss); + VECI(MIPS3_XTLB_MISS, TLBMiss); VECI(MIPS3_CACHE_ERR, Cache); VECI(MIPS3_GEN, Exception); @@ -156,7 +156,7 @@ */ wtf->wtf_class = MIPS_R4000; wtf->wtf_type = "XZ"; - wtf->wtf_ntlbs = 2; /* XX Find the right value. */ + wtf->wtf_ntlbs = 16; /* XX Find the right value. */ wtf->wtf_fpu = "YC"; #if 0 unsigned long cpu_class; ==== //depot/projects/mips2/src/sys/mips/mips/exception.S#3 (text+ko) ==== @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#2 $ + * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#3 $ */ #include "opt_ddb.h" @@ -213,13 +213,20 @@ */ /* VPN2 = (VA >> page_shift) / 2 */ - la k1, VM_MIN_ADDRESS + la k1, VM_MIN_KERNEL_ADDRESS subu k0, k0, k1 srl k0, PAGE_SHIFT + 1 + + /* + * XXXMIPS: + * offset == VPN2 * sizeof(pt_entry_t) * 2 + * dividing by 2 and multiplying by 2 we're + * getting even page number. MIPS TLB stuff + * works with couples of VP. + */ sll k0, 2 + 1 la k1, kptmap - /* * Find the page table, and index it. */ ==== //depot/projects/mips2/src/sys/mips/mips/machdep.c#15 (text+ko) ==== @@ -74,6 +74,7 @@ int cold = 1; int clocks_running; long realmem = 0; +extern int *end; static struct pcpu pcpu0; struct pcpu *pcpup = &pcpu0; @@ -90,10 +91,28 @@ void mips_init(void) { + int i; + printf("mips_init() executed!\n"); + /* + * "memsize" env variable is in megabytes. + * realmem is in pages. + */ + realmem = btoc(64 << 20); + + for(i = 0; i<10; i++) + phys_avail[i] = 0; + + /* phys_avail regions are in bytes */ + phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end); + phys_avail[1] = ctob(realmem); + + physmem = realmem; + /* * This one is called from subr_param.c. */ + init_param1(); init_param2(physmem); /* * This one lies in cpu.c. @@ -102,14 +121,11 @@ /* * This is from pmap.c. */ -#if 0 pmap_bootstrap(); -#endif /* * XXXMIPS: Change this once I'll make sure pagetables are working * correctly. */ -#if 0 proc_linkup(&proc0, &ksegrp0, &thread0); thread0.td_kstack = kstack0; pcpu_init(pcpup, 0, sizeof(struct pcpu)); @@ -120,7 +136,6 @@ #ifdef DDB kdb_init(); #endif -#endif } void ==== //depot/projects/mips2/src/sys/mips/mips/pmap.c#5 (text+ko) ==== @@ -208,15 +208,11 @@ static pt_entry_t* pmap_pte(pmap_t pmap, vm_offset_t va) { -#ifdef notyet if (pmap != kernel_pmap) panic("non kernel pmap unsupported"); if (pmap == NULL || pmap->pm_lev1 == NULL) return NULL; return tlb_pte_find(pmap->pm_lev1, va); -#else - return NULL; -#endif } @@ -304,14 +300,13 @@ /* * Initialise TLB management, and have it allocate page tables. */ -#ifdef notyet tlb_bootstrap(realmem, pmap_steal_memory); -#endif for (i = 0; phys_avail[i+2]; i+= 2) /* find non-empty ones */; virtual_avail = VM_MIN_KERNEL_ADDRESS; - virtual_end = virtual_avail + (phys_avail[i+1] - phys_avail[0]); + virtual_end = VM_MAX_KERNEL_ADDRESS; + kernel_vm_end = virtual_end; /* @@ -370,7 +365,7 @@ { vm_page_t m; - m = PHYS_TO_VM_PAGE(MIPS_KSEG1_TO_PHYS((vm_offset_t)mem)); + m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS((vm_offset_t)mem)); vm_page_lock_queues(); vm_page_free(m); vm_page_unlock_queues(); @@ -676,7 +671,16 @@ vm_offset_t pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) { - return MIPS_PHYS_TO_KSEG1(start); + vm_offset_t sva = *virt; + vm_offset_t va = sva; + while (start < end) { + pmap_kenter(va, start); + va += PAGE_SIZE; + start += PAGE_SIZE; + } + *virt = va; + + return (sva); } void @@ -726,7 +730,7 @@ vm_page_unlock_queues(); VM_OBJECT_UNLOCK(pmap->pm_pteobj); - pmap->pm_lev1 = (pt_entry_t*) MIPS_PHYS_TO_KSEG1(VM_PAGE_TO_PHYS(lev1pg)); + pmap->pm_lev1 = (pt_entry_t*) MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(lev1pg)); /* install self-referential address mapping entry (not PG_ASM) */ pmap->pm_lev1[PTLEV1I] = pmap_phys_to_pte(VM_PAGE_TO_PHYS(lev1pg)) @@ -1646,7 +1650,8 @@ void * pmap_mapdev(vm_offset_t pa, vm_size_t size) { - return (void *)MIPS_PHYS_TO_KSEG1(pa); + /* XXXMIPS: return (void *)MIPS_PHYS_TO_KSEG1(pa); */ + return 0; } void @@ -1735,10 +1740,7 @@ if (pmap->pm_asidgen != PCPU_GET(current_asidgen)) pmap_get_asid(pmap); -#ifdef notyet - /* XXX: we need mips32-friendly register macros */ mips_wr_entryhi(pmap->pm_asid); -#endif pmap_active = pmap; atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); ==== //depot/projects/mips2/src/sys/mips/mips/support.S#5 (text+ko) ==== @@ -27,120 +27,300 @@ */ #include <machine/asm.h> #include <machine/asmacros.h> +#include <machine/cpuregs.h> __FBSDID("$FreeBSD$"); #include "assym.s" /* - * XXXMIPS: Implement these routines + * If an unaligned access occurs, someone is doing something wrong, don't + * fixup here, let things happen elsewhere, if at all. We shouldn't suck. + * We should also use the BD slot properly, so this whole file is covered + * by a .set noreorder */ -ENTRY(bcmp) - break -END(bcmp) + .set noreorder +/* + * The normal C bcopy(3), + * void bcopy(<a0>const void *src, <a1>void *dst, <a2>size_t len) + */ ENTRY(bcopy) - break + beqz a2, 2f + nop +1: subu a2, 1 + lbu t0, 0(a0) + addu a0, 1 + sb t0, 0(a1) + bnezl a2, 1b + addu a1, 1 +2: jr ra + nop END(bcopy) -ENTRY(bintr) - break -END(bintr) +/* XXXMIPS: test/optimize this function. + * The normal C bcmp(3), + * <v0>int bcmp(<a0>const void *b1, <a1>const void *b2, <a2>size_t len) + */ +ENTRY(bcmp) + beqz a2, 2f + li v0, 0 +1: subu a2, 1 + lbu t0, 0(a0) + lbu t1, 0(a1) + bne t0, t1, 3f + addu a0, 1 + addu a1, 1 + bnezl a2, 1b + nop +2: li v0, 1 +3: jr ra + nop +END(bcmp) -ENTRY(btrap) - break -END(btrap) - +/* + * The normal C bzero(3), + * void bzero(<a0>void *str, <a1>size_t len) + */ ENTRY(bzero) - break + beqz a1, 2f + nop +1: subu a1, 1 + sb zero, 0(a0) + bnezl a1, 1b + addu a0, 1 +2: jr ra + nop END(bzero) -ENTRY(eintr) - break -END(eintr) - -ENTRY(etrap) - break -END(etrap) - +/* + * The normal C memcpy(3), + * <v0>void *memcpy(<a0>void *dst, <a1>const void *src, <a2>size_t len) + */ ENTRY(memcpy) - break + beqz a2, 2f + move v0, a0 +1: subu a2, 1 + lbu t0, 0(a1) + addu a1, 1 + sb t0, 0(a0) + bnezl a2, 1b + addu a0, 1 +2: jr ra + nop END(memcpy) -ENTRY(memmove) - break -END(memmove) +/* + * Stubs for store(9) XXX + subyte() Stores a byte of data to the user-space address base. -ENTRY(memset) - break -END(memset) + susword() Stores a short word of data to the user-space address base. -ENTRY(user) - break -END(user) + suswintr() Stores a short word of data to the user-space address base. + This function is safe to call during an interrupt context. -ENTRY(setjmp) - break -END(setjmp) + suword() Stores a word of data to the user-space address base. + */ -ENTRY(longjmp) - break -END(longjmp) - +/* + * subyte(9) + * <v0>int subyte(<a0>void *addr, <a1>int byte) + */ ENTRY(subyte) - break + li v0, -1 + jr ra + nop END(subyte) +/* + * susword(9) + * <v0>int susword(<a0>void *addr, <a1>int shortword) + */ ENTRY(susword) - break + li v0, -1 + jr ra + nop END(susword) +/* + * suswintr(9) + * <v0>int suswintr(<a0>void *addr, <a1>int shortword) + */ ENTRY(suswintr) - break + li v0, -1 + jr ra + nop END(suswintr) +/* + * suword(9) + * <v0>int suword(<a0>void *addr, <a1>long word) + */ ENTRY(suword) - break + li v0, -1 + jr ra + nop END(suword) +/* + * suword32(9) + * <v0>int suword32(<a0>void *addr, <a1>int word) + */ ENTRY(suword32) - break + li v0, -1 + jr ra + nop END(suword32) +/* + * suword64(9) + * <v0>int suword64(<a0>void *addr, <a1>long word) + */ ENTRY(suword64) - break + li v0, -1 + jr ra + nop END(suword64) +/* + * Stubs for fetch(9) XXX + fubyte() Fetches a byte of data from the user-space address base. + + fusword() Fetches a short word of data from the user-space address + base. + + fuswintr() Fetches a short word of data from the user-space address + base. This function is safe to call during an interrupt con- + text. + + fuword() Fetches a word (long) of data from the user-space address base. + fuword32() Fetches a word (int, 32-bits) of data from the user-space address base. + */ + +/* + * fubyte(9) + * <v0>int fubyte(<a0>const void *addr) + */ ENTRY(fubyte) - break + li v0, -1 + jr ra + nop END(fubyte) +/* + * fusword(9) + * <v0>int fusword(<a0>const void *addr) + */ ENTRY(fusword) - break + li v0, -1 + jr ra + nop END(fusword) +/* + * fuswintr(9) + * <v0>int fuswintr(<a0>const void *addr) + */ ENTRY(fuswintr) - break + li v0, -1 + jr ra + nop END(fuswintr) +/* + * fuword(9) + * <v0>long fuword(<a0>const void *addr) + */ ENTRY(fuword) - break + li v0, -1 + jr ra + nop END(fuword) +/* + * fuword32(9) + * <v0>int fuword32(<a0>const void *addr) + */ ENTRY(fuword32) - break + li v0, -1 + jr ra + nop END(fuword32) +/* + * Stubs for copy(9) XXX + copyin() Copies len bytes of data from the user-space address uaddr + to the kernel-space address kaddr. + + copyout() Copies len bytes of data from the kernel-space address + kaddr to the user-space address uaddr. + */ +/* + * copyin(9) + * <v0>int copyin(<a0>const void *useraddr, <a1>void *kernaddr, <a2>size_t len) + */ ENTRY(copyin) - break + jr ra + nop END(copyin) +/* + * copyout(9) + * <v0>int copyout(<a0>const void *kernaddr, <a1>void *useraddr, <a2>size_t len) + */ ENTRY(copyout) - break + jr ra + nop END(copyout) +/* + * setjmp(9) + * <v0>int setjmp(<a0>jmp_buf) + */ +ENTRY(setjmp) + mfc0 t0, MIPS_COP_0_STATUS + sw s0, PCB_REG_S0(a0) + sw s1, PCB_REG_S1(a0) + sw s2, PCB_REG_S2(a0) + sw s3, PCB_REG_S3(a0) + sw s4, PCB_REG_S4(a0) + sw s5, PCB_REG_S5(a0) + sw s6, PCB_REG_S6(a0) + sw s7, PCB_REG_S7(a0) + sw s8, PCB_REG_S8(a0) + sw sp, PCB_REG_SP(a0) + sw t0, PCB_REG_SR(a0) + sw ra, PCB_REG_RA(a0) + li v0, 0 + jr ra + nop +END(setjmp) + +/* + * longjmp(9) + * void longjmp(<a0>jmp_buf, <a1>retval) + */ +ENTRY(longjmp) + lw s0, PCB_REG_S0(a0) + lw s1, PCB_REG_S1(a0) + lw s2, PCB_REG_S2(a0) + lw s3, PCB_REG_S3(a0) + lw s4, PCB_REG_S4(a0) + lw s5, PCB_REG_S5(a0) + lw s6, PCB_REG_S6(a0) + lw s7, PCB_REG_S7(a0) + lw s8, PCB_REG_S8(a0) + lw sp, PCB_REG_SP(a0) + lw ra, PCB_REG_RA(a0) + lw t0, PCB_REG_SR(a0) + mtc0 t0, MIPS_COP_0_STATUS + move v0, a1 + jr ra + nop +END(longjmp) + /* * XXXMIPS: ==== //depot/projects/mips2/src/sys/mips/mips/tlb.c#6 (text+ko) ==== @@ -83,8 +83,10 @@ /* * Set up KPT. + * XXXMIPS: Direct-mapped page table. Interim solution while getting + * new pmap on it's way. */ - kptsize = pages; + kptsize = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) >> PAGE_SHIFT; kptmap = (pt_entry_t *) (*ptalloc)(kptsize * sizeof (pt_entry_t)); /* @@ -141,7 +143,7 @@ pmap, (u_long)va, (u_long)pa, (u_long)bits); *pte &= PG_G; *pte |= MIPS_PA_TO_PFN(pa) | bits; - *pte |= PG_C_CNC; /* Cacheable noncoherent. */ + *pte |= PG_C_UNCACHED; } void @@ -179,10 +181,7 @@ int i; va &= ~PAGE_MASK; -#ifdef CPU_MIPS64 ehi = MIPS_HI_ENTRY(va, /*asid*/0); -#endif - ehi = 0; mips_wr_entryhi(ehi); mips_tlbp(); i = mips_rd_index(); @@ -215,12 +214,8 @@ /* Bogus VPN2. */ ehi = MIPS_KSEG1_END + 2 * i * PAGE_SIZE; mips_wr_index(i); -#ifdef CPU_MIPS64 mips_wr_entrylo0(0); mips_wr_entrylo1(0); -#else - mips_wr_entrylow(0); -#endif mips_wr_entryhi(ehi); mips_tlbwi(); } @@ -232,10 +227,7 @@ int i; va &= ~PAGE_MASK; -#ifdef CPU_MIPS64 ehi = MIPS_HI_ENTRY(va, /*asid*/0); -#endif - ehi = 0; mips_wr_entryhi(ehi); mips_tlbp(); i = mips_rd_index(); ==== //depot/projects/mips2/src/sys/mips/mips/vm_machdep.c#3 (text+ko) ==== @@ -45,6 +45,10 @@ #include <sys/lock.h> #include <sys/mutex.h> +#include <machine/cpu.h> +#include <machine/cpufunc.h> +#include <machine/frame.h> + #include <vm/vm.h> #include <vm/vm_extern.h> #include <vm/vm_kern.h> @@ -58,25 +62,25 @@ cpu_fork(register struct thread *td1, register struct proc *p2, struct thread *td2, int flags) { - + panic("%s", __func__); } void cpu_thread_swapin(struct thread *td) { - + panic("%s", __func__); } void cpu_thread_swapout(struct thread *td) { - + panic("%s", __func__); } void sf_buf_free(struct sf_buf *sf) { - + panic("%s", __func__); } #if 0 static void @@ -89,61 +93,68 @@ struct sf_buf * sf_buf_alloc(struct vm_page *m, int flags) { + panic("%s", __func__); return (NULL); } void cpu_set_upcall(struct thread *td, struct thread *td0) { - + panic("%s", __func__); } void cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg, stack_t *stack) { - + panic("%s", __func__); } int cpu_set_user_tls(struct thread *td, void *tls_base) { + panic("%s", __func__); return (0); } void cpu_thread_exit(struct thread *td) { - + panic("%s", __func__); } void cpu_thread_setup(struct thread *td) { - + td->td_pcb = + (struct pcb *)(td->td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; + td->td_frame = (struct trapframe *)td->td_pcb - 1; + td->td_pcb->pcb_regs[PCB_REG_SR] = MIPS_SR_KX | MIPS_SR_INT_IE; + /* Stack pointer. */ + td->td_pcb->pcb_regs[PCB_REG_SP] = (register_t)_ALIGN(td->td_frame - 1); } void cpu_thread_clean(struct thread *td) { - + panic("%s", __func__); } void cpu_set_fork_handler(struct thread *td, void (*func)(void *), void *arg) { - + panic("%s", __func__); } void swi_vm(void *dummy) { - + panic("%s", __func__); } void cpu_exit(struct thread *td) { - + panic("%s", __func__); }
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