Date: Tue, 11 Mar 2014 17:02:49 +0800 From: Ganbold Tsagaankhuu <ganbold@gmail.com> To: "freebsd-arm@freebsd.org" <freebsd-arm@freebsd.org> Subject: Re: Enabling second core on A20 (Dual core Cortex A7) Message-ID: <CAGtf9xNk89gsGTK72_890xT66jzsXZ8O0eibn6L1_vFEi%2B9zJA@mail.gmail.com> In-Reply-To: <CAGtf9xOiSU65FE6rNCQukbqOPHZ_%2B=EE85w5je3EdFwxudMfjw@mail.gmail.com> References: <CAGtf9xOiSU65FE6rNCQukbqOPHZ_%2B=EE85w5je3EdFwxudMfjw@mail.gmail.com>
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On Tue, Mar 11, 2014 at 9:24 AM, Ganbold Tsagaankhuu <ganbold@gmail.com>wrote: > Hi, > > I'm trying to enable SMP on cubieboard2 which has A20 SoC, dual core > Cortex A7. > However it boots with "WARNING: Some AP's failed to start" msg. > > The code is at: > > https://github.com/tsgan/allwinner_a10/blob/master/a20/a20_mp.c > Replying to myself. It was my fault, I should be using physical address for the register instead of virtual. Now I've got second core enabled :) However there happens spurious interrupt detected [0x000003ff] from time to time. Ganbold > > > Linux code is at: > > > https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/arch/arm/mach-sun7i/platsmp.c > > https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/arch/arm/mach-sun7i/headsmp.S > > My asm foo is not good so I thought I'd better ask if it could be related > to > locore.S or early initialization codes for enabling SMP. > > ARM Cortex A7 MPCore Tech ref manual says (page 40): > > "To power up the processor, apply the following sequence: > 1. Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW. Ensure > DBGPWRDUP is held LOW to prevent any external debug access to the > processor. > 2. Apply power to the Vcore power domain. Keep the state of the signals > nCOREPORESET, L1RSTDISABLE and DBGPWRDUP LOW. > 3. When the power domain has stabilized and reset has been asserted for > four or > more cycles, > release the processor output clamps. > 4. De-assert resets. > 5. Assert DBGPWRDUP HIGH to allow external debug access to the processor. > 6. If required use software to restore the state of the processor prior to > power-down. > 7. Assert ACTLR.SMP bit HIGH for SMP mode. Continue a normal power-on reset > sequence." > > It seems setting ACTLR smp bit is taken place in cortexa_setup() of > cpufunc.c > which seems to be called before platform_mp_start_ap(). > But I maybe overlooked this, or the problem could be somewhere else, so > correct me if I'm wrong here. > > Also it seems atomic_add_rel_32(&mp_naps, 1) doesn't increase mp_naps and > cpu_mp_start() of mp_machdep.c complaines with "WARNING: Some AP's failed > to > start" msg at boot. > It could be related maybe because ACTLR smp bit is not set, since A20 > CPU0/CPU1 > status register reading says SMP mode is still not set. A20 doc is not > good so I > had to look for linux codes. > > Sysctl reading says: > > root@arm:~ # sysctl -a|grep cpu > kern.sched.cpusetsize: 4 > kern.ccpu: 1948 > kern.smp.maxcpus: 4 > kern.smp.cpus: 1 > net.inet.tcp.per_cpu_timers: 0 > debug.cpufreq.lowest: 0 > debug.cpufreq.verbose: 0 > hw.ncpu: 2 > > So am I missing something in my code or are there some places where I > should put > debug printf checking for variables, register values etc. ? > I appreciate if someone can point me to the right direction. > > Boot log at: > > https://github.com/tsgan/allwinner_a10/blob/master/a20/dmesg_smp.txt > > thanks a lot, > > Ganbold >
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