From owner-svn-src-all@freebsd.org Tue Oct 31 23:17:19 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 097E3E3EA88; Tue, 31 Oct 2017 23:17:19 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CD4CB68390; Tue, 31 Oct 2017 23:17:18 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v9VNHHEU069091; Tue, 31 Oct 2017 23:17:17 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v9VNHH7W069090; Tue, 31 Oct 2017 23:17:17 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201710312317.v9VNHH7W069090@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 31 Oct 2017 23:17:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325251 - head/sys/arm64/arm64 X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/sys/arm64/arm64 X-SVN-Commit-Revision: 325251 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Oct 2017 23:17:19 -0000 Author: andrew Date: Tue Oct 31 23:17:17 2017 New Revision: 325251 URL: https://svnweb.freebsd.org/changeset/base/325251 Log: Allocate the ITS translation table with a 64k page alignment. This is the largest alignment the ITS can require. This fixes a bug with the ARM Architecture Envelope Model (AEM) where it only allows 64k pages so will fail to attach the ITS device when this table is not sufficiently aligned. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/gicv3_its.c Modified: head/sys/arm64/arm64/gicv3_its.c ============================================================================== --- head/sys/arm64/arm64/gicv3_its.c Tue Oct 31 22:12:14 2017 (r325250) +++ head/sys/arm64/arm64/gicv3_its.c Tue Oct 31 23:17:17 2017 (r325251) @@ -457,7 +457,7 @@ gicv3_its_table_init(device_t dev, struct gicv3_its_so /* Allocate the table */ table = (vm_offset_t)contigmalloc(npages * PAGE_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, - PAGE_SIZE, 0); + PAGE_SIZE_64K, 0); sc->sc_its_ptab[i].ptab_vaddr = table; sc->sc_its_ptab[i].ptab_size = npages * PAGE_SIZE;