Date: Thu, 14 Aug 2014 23:17:34 +0000 (UTC) From: Warner Losh <imp@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r270006 - head/sys/arm/at91 Message-ID: <201408142317.s7ENHYig069389@svn.freebsd.org>
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Author: imp Date: Thu Aug 14 23:17:33 2014 New Revision: 270006 URL: http://svnweb.freebsd.org/changeset/base/270006 Log: Print the symbolic bit names for the status when we get a timeout. Modified: head/sys/arm/at91/at91_mci.c head/sys/arm/at91/at91_mcireg.h Modified: head/sys/arm/at91/at91_mci.c ============================================================================== --- head/sys/arm/at91/at91_mci.c Thu Aug 14 22:52:05 2014 (r270005) +++ head/sys/arm/at91/at91_mci.c Thu Aug 14 23:17:33 2014 (r270006) @@ -1210,8 +1210,8 @@ at91_mci_intr(void *arg) */ if (cmd->opcode != 8) { device_printf(sc->dev, - "IO error; status MCI_SR = 0x%x cmd opcode = %d%s\n", - sr, cmd->opcode, + "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n", + sr, MCI_SR_BITSTRING, cmd->opcode, (cmd->opcode != 12) ? "" : (sc->flags & CMD_MULTIREAD) ? " after read" : " after write"); at91_mci_reset(sc); Modified: head/sys/arm/at91/at91_mcireg.h ============================================================================== --- head/sys/arm/at91/at91_mcireg.h Thu Aug 14 22:52:05 2014 (r270005) +++ head/sys/arm/at91/at91_mcireg.h Thu Aug 14 23:17:33 2014 (r270006) @@ -118,6 +118,30 @@ #define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */ #define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */ +/* TXRDY,DTIP,ENDTX,TXBUFE,RTOE */ + +#define MCI_SR_BITSTRING \ + "\020" \ + "\001CMDRDY" \ + "\002RXRDY" \ + "\003TXRDY" \ + "\004BLKE" \ + "\005DTIP" \ + "\006NOTBUSY" \ + "\007ENDRX" \ + "\010ENDTX" \ + "\017RXBUFF" \ + "\020TXBUFE" \ + "\021RINDE" \ + "\022RDIRE" \ + "\023RCRCE" \ + "\024RENDE" \ + "\025RTOE" \ + "\026DCRCE" \ + "\027DTOE" \ + "\037OVRE" \ + "\040UNRE" + /* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */ /* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */ /* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */
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