From owner-svn-src-head@freebsd.org Thu Nov 12 19:07:04 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C64DFA2D722; Thu, 12 Nov 2015 19:07:04 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 9E9BF1EFA; Thu, 12 Nov 2015 19:07:04 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tACJ73Ax035411; Thu, 12 Nov 2015 19:07:03 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tACJ73tk035409; Thu, 12 Nov 2015 19:07:03 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201511121907.tACJ73tk035409@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: "Conrad E. Meyer" Date: Thu, 12 Nov 2015 19:07:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290725 - head/sys/dev/ntb/ntb_hw X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Nov 2015 19:07:04 -0000 Author: cem Date: Thu Nov 12 19:07:03 2015 New Revision: 290725 URL: https://svnweb.freebsd.org/changeset/base/290725 Log: NTB: MFV 8b782fab: unify translation addresses There is no need for the upstream and downstream addresses to be different for the NTB configs. Go to using a single set of address. It is still possible to configure them differently using module parameter override however (CEM: tunable). Authored by: Dave Jiang Reviewed by: Allen Hubbe Reviewed by: Jon Mason Obtained from: Linux (Dual BSD/GPL driver) Sponsored by: EMC / Isilon Storage Division Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c head/sys/dev/ntb/ntb_hw/ntb_regs.h Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c ============================================================================== --- head/sys/dev/ntb/ntb_hw/ntb_hw.c Thu Nov 12 18:42:06 2015 (r290724) +++ head/sys/dev/ntb/ntb_hw/ntb_hw.c Thu Nov 12 19:07:03 2015 (r290725) @@ -415,19 +415,19 @@ static const struct ntb_xlat_reg xeon_se }; static struct ntb_b2b_addr xeon_b2b_usd_addr = { - .bar0_addr = XEON_B2B_BAR0_USD_ADDR, - .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64, - .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64, - .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32, - .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32, + .bar0_addr = XEON_B2B_BAR0_ADDR, + .bar2_addr64 = XEON_B2B_BAR2_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_ADDR32, }; static struct ntb_b2b_addr xeon_b2b_dsd_addr = { - .bar0_addr = XEON_B2B_BAR0_DSD_ADDR, - .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64, - .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64, - .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32, - .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32, + .bar0_addr = XEON_B2B_BAR0_ADDR, + .bar2_addr64 = XEON_B2B_BAR2_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_ADDR32, }; SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, @@ -1346,18 +1346,18 @@ configure_atom_secondary_side_bars(struc if (ntb->dev_type == NTB_DEV_USD) { ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, - XEON_B2B_BAR2_DSD_ADDR64); + XEON_B2B_BAR2_ADDR64); ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, - XEON_B2B_BAR4_DSD_ADDR64); - ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64); - ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64); + XEON_B2B_BAR4_ADDR64); + ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); } else { ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, - XEON_B2B_BAR2_USD_ADDR64); + XEON_B2B_BAR2_ADDR64); ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, - XEON_B2B_BAR4_USD_ADDR64); - ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64); - ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64); + XEON_B2B_BAR4_ADDR64); + ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); + ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); } } Modified: head/sys/dev/ntb/ntb_hw/ntb_regs.h ============================================================================== --- head/sys/dev/ntb/ntb_hw/ntb_regs.h Thu Nov 12 18:42:06 2015 (r290724) +++ head/sys/dev/ntb/ntb_hw/ntb_regs.h Thu Nov 12 19:07:03 2015 (r290725) @@ -154,16 +154,11 @@ #define ATOM_PPD_DEV_TYPE 0x1000 /* All addresses are in low 32-bit space so 32-bit BARs can function */ -#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull -#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull -#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull -#define XEON_B2B_BAR4_USD_ADDR32 0x20000000ull -#define XEON_B2B_BAR5_USD_ADDR32 0x40000000ull -#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull -#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull -#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull -#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000ull -#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000ull +#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull +#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull +#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull +#define XEON_B2B_BAR4_ADDR32 0x20000000ull +#define XEON_B2B_BAR5_ADDR32 0x40000000ull /* The peer ntb secondary config space is 32KB fixed size */ #define XEON_B2B_MIN_SIZE 0x8000