From owner-p4-projects@FreeBSD.ORG Tue Oct 23 07:12:06 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id A56BDB2C; Tue, 23 Oct 2012 07:12:06 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 560D1B2A for ; Tue, 23 Oct 2012 07:12:06 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 3A47D8FC0C for ; Tue, 23 Oct 2012 07:12:06 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q9N7C5T4069103 for ; Tue, 23 Oct 2012 07:12:06 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q9N7C55T069100 for perforce@freebsd.org; Tue, 23 Oct 2012 07:12:05 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Tue, 23 Oct 2012 07:12:05 GMT Message-Id: <201210230712.q9N7C55T069100@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson Subject: PERFORCE change 218947 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.14 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Oct 2012 07:12:06 -0000 http://p4web.freebsd.org/@@218947?ac=10 Change 218947 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/10/23 07:11:10 Prefer the name "CHERI" to "CP2" throughout the CHERI code, as it makes it easier to search for, and more clear that it's CHERI-specific rather than a generic COP2 function in MIPS. Use CHERI ISAv2's immediate arguments to clc and csc to avoid treading on a MIPS temporary register during exception handling, embedding offsets into the CHERI register frame structure directly, as is done for native MIPS registers. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#16 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#9 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#8 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#7 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/pcb.h#6 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/exception.S#10 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/genassym.c#4 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/swtch.S#9 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#16 (text+ko) ==== @@ -67,7 +67,7 @@ */ void -cp2_capability_set(struct chericap *cp, uint32_t perms, +cheri_capability_set(struct chericap *cp, uint32_t perms, void *otypep /* eaddr */, void *basep, uint64_t length) { register_t s; @@ -88,7 +88,7 @@ } static void -cp2_capability_clear(struct chericap *cp) +cheri_capability_clear(struct chericap *cp) { /* @@ -107,26 +107,26 @@ * contexts. */ void -cp2_capability_set_priv(struct chericap *cp) +cheri_capability_set_priv(struct chericap *cp) { - cp2_capability_set(cp, CHERI_CAP_PRIV_PERMS, CHERI_CAP_PRIV_OTYPE, + cheri_capability_set(cp, CHERI_CAP_PRIV_PERMS, CHERI_CAP_PRIV_OTYPE, CHERI_CAP_PRIV_BASE, CHERI_CAP_PRIV_LENGTH); } void -cp2_capability_set_user(struct chericap *cp) +cheri_capability_set_user(struct chericap *cp) { - cp2_capability_set(cp, CHERI_CAP_USER_PERMS, CHERI_CAP_USER_OTYPE, + cheri_capability_set(cp, CHERI_CAP_USER_PERMS, CHERI_CAP_USER_OTYPE, CHERI_CAP_USER_BASE, CHERI_CAP_USER_LENGTH); } void -cp2_capability_set_null(struct chericap *cp) +cheri_capability_set_null(struct chericap *cp) { - cp2_capability_clear(cp); + cheri_capability_clear(cp); } /* @@ -140,7 +140,7 @@ * XXXRW: Compiler should be providing us with the temporary register. */ void -cp2_capability_copy(struct chericap *cp_to, struct chericap *cp_from) +cheri_capability_copy(struct chericap *cp_to, struct chericap *cp_from) { register_t s; @@ -151,52 +151,52 @@ * temporary preserved during kernel execution to avoid this. */ s = intr_disable(); - cp2_capability_load(CHERI_CR_KR1C, cp_from); - cp2_capability_store(CHERI_CR_KR1C, cp_to); + cheri_capability_load(CHERI_CR_KR1C, cp_from); + cheri_capability_store(CHERI_CR_KR1C, cp_to); intr_restore(s); } void -cp2_context_copy(struct cp2_frame *cf_destp, struct cp2_frame *cf_srcp) +cheri_context_copy(struct cheri_frame *cf_destp, struct cheri_frame *cf_srcp) { - cp2_capability_copy(&cf_destp->cf_c0, &cf_srcp->cf_c0); - cp2_capability_copy(&cf_destp->cf_c1, &cf_srcp->cf_c1); - cp2_capability_copy(&cf_destp->cf_c2, &cf_srcp->cf_c2); - cp2_capability_copy(&cf_destp->cf_c3, &cf_srcp->cf_c3); - cp2_capability_copy(&cf_destp->cf_c4, &cf_srcp->cf_c4); - cp2_capability_copy(&cf_destp->cf_c5, &cf_srcp->cf_c5); - cp2_capability_copy(&cf_destp->cf_c6, &cf_srcp->cf_c6); - cp2_capability_copy(&cf_destp->cf_c7, &cf_srcp->cf_c7); - cp2_capability_copy(&cf_destp->cf_c8, &cf_srcp->cf_c8); - cp2_capability_copy(&cf_destp->cf_c9, &cf_srcp->cf_c9); - cp2_capability_copy(&cf_destp->cf_c10, &cf_srcp->cf_c10); - cp2_capability_copy(&cf_destp->cf_c11, &cf_srcp->cf_c11); - cp2_capability_copy(&cf_destp->cf_c12, &cf_srcp->cf_c12); - cp2_capability_copy(&cf_destp->cf_c13, &cf_srcp->cf_c13); - cp2_capability_copy(&cf_destp->cf_c14, &cf_srcp->cf_c14); - cp2_capability_copy(&cf_destp->cf_c15, &cf_srcp->cf_c15); - cp2_capability_copy(&cf_destp->cf_c16, &cf_srcp->cf_c16); - cp2_capability_copy(&cf_destp->cf_c17, &cf_srcp->cf_c17); - cp2_capability_copy(&cf_destp->cf_c18, &cf_srcp->cf_c18); - cp2_capability_copy(&cf_destp->cf_c19, &cf_srcp->cf_c19); - cp2_capability_copy(&cf_destp->cf_c20, &cf_srcp->cf_c20); - cp2_capability_copy(&cf_destp->cf_c21, &cf_srcp->cf_c21); - cp2_capability_copy(&cf_destp->cf_c22, &cf_srcp->cf_c22); - cp2_capability_copy(&cf_destp->cf_c23, &cf_srcp->cf_c23); - cp2_capability_copy(&cf_destp->cf_c24, &cf_srcp->cf_c24); - cp2_capability_copy(&cf_destp->cf_c26, &cf_srcp->cf_c26); + cheri_capability_copy(&cf_destp->cf_c0, &cf_srcp->cf_c0); + cheri_capability_copy(&cf_destp->cf_c1, &cf_srcp->cf_c1); + cheri_capability_copy(&cf_destp->cf_c2, &cf_srcp->cf_c2); + cheri_capability_copy(&cf_destp->cf_c3, &cf_srcp->cf_c3); + cheri_capability_copy(&cf_destp->cf_c4, &cf_srcp->cf_c4); + cheri_capability_copy(&cf_destp->cf_c5, &cf_srcp->cf_c5); + cheri_capability_copy(&cf_destp->cf_c6, &cf_srcp->cf_c6); + cheri_capability_copy(&cf_destp->cf_c7, &cf_srcp->cf_c7); + cheri_capability_copy(&cf_destp->cf_c8, &cf_srcp->cf_c8); + cheri_capability_copy(&cf_destp->cf_c9, &cf_srcp->cf_c9); + cheri_capability_copy(&cf_destp->cf_c10, &cf_srcp->cf_c10); + cheri_capability_copy(&cf_destp->cf_c11, &cf_srcp->cf_c11); + cheri_capability_copy(&cf_destp->cf_c12, &cf_srcp->cf_c12); + cheri_capability_copy(&cf_destp->cf_c13, &cf_srcp->cf_c13); + cheri_capability_copy(&cf_destp->cf_c14, &cf_srcp->cf_c14); + cheri_capability_copy(&cf_destp->cf_c15, &cf_srcp->cf_c15); + cheri_capability_copy(&cf_destp->cf_c16, &cf_srcp->cf_c16); + cheri_capability_copy(&cf_destp->cf_c17, &cf_srcp->cf_c17); + cheri_capability_copy(&cf_destp->cf_c18, &cf_srcp->cf_c18); + cheri_capability_copy(&cf_destp->cf_c19, &cf_srcp->cf_c19); + cheri_capability_copy(&cf_destp->cf_c20, &cf_srcp->cf_c20); + cheri_capability_copy(&cf_destp->cf_c21, &cf_srcp->cf_c21); + cheri_capability_copy(&cf_destp->cf_c22, &cf_srcp->cf_c22); + cheri_capability_copy(&cf_destp->cf_c23, &cf_srcp->cf_c23); + cheri_capability_copy(&cf_destp->cf_c24, &cf_srcp->cf_c24); + cheri_capability_copy(&cf_destp->cf_c26, &cf_srcp->cf_c26); /* * XXXRW: not in CHERI ISAv2: - * cp2_capability_copy(&cf_destp->cf_tsc, &cf_srcp->cf_tsc); + * cheri_capability_copy(&cf_destp->cf_tsc, &cf_srcp->cf_tsc); */ - cp2_capability_copy(&cf_destp->cf_pcc, &cf_srcp->cf_pcc); + cheri_capability_copy(&cf_destp->cf_pcc, &cf_srcp->cf_pcc); } void cheri_exec_setregs(struct thread *td) { - struct cp2_frame *cfp; + struct cheri_frame *cfp; /* * XXXRW: Experimental CHERI ABI initialises $c0 with full user @@ -204,42 +204,42 @@ * no rights at all. The runtime linker/compiler/application can * propagate around rights as required. */ - cfp = &td->td_pcb->pcb_cp2frame; - cp2_capability_set_user(&cfp->cf_c0); - cp2_capability_set_null(&cfp->cf_c1); - cp2_capability_set_null(&cfp->cf_c2); - cp2_capability_set_null(&cfp->cf_c3); - cp2_capability_set_null(&cfp->cf_c4); - cp2_capability_set_null(&cfp->cf_c5); - cp2_capability_set_null(&cfp->cf_c6); - cp2_capability_set_null(&cfp->cf_c7); - cp2_capability_set_null(&cfp->cf_c8); - cp2_capability_set_null(&cfp->cf_c9); - cp2_capability_set_null(&cfp->cf_c10); - cp2_capability_set_null(&cfp->cf_c11); - cp2_capability_set_null(&cfp->cf_c12); - cp2_capability_set_null(&cfp->cf_c13); - cp2_capability_set_null(&cfp->cf_c14); - cp2_capability_set_null(&cfp->cf_c15); - cp2_capability_set_null(&cfp->cf_c16); - cp2_capability_set_null(&cfp->cf_c17); - cp2_capability_set_null(&cfp->cf_c18); - cp2_capability_set_null(&cfp->cf_c19); - cp2_capability_set_null(&cfp->cf_c20); - cp2_capability_set_null(&cfp->cf_c21); - cp2_capability_set_null(&cfp->cf_c22); - cp2_capability_set_null(&cfp->cf_c23); - cp2_capability_set_null(&cfp->cf_c24); - cp2_capability_set_null(&cfp->cf_c26); + cfp = &td->td_pcb->pcb_cheriframe; + cheri_capability_set_user(&cfp->cf_c0); + cheri_capability_set_null(&cfp->cf_c1); + cheri_capability_set_null(&cfp->cf_c2); + cheri_capability_set_null(&cfp->cf_c3); + cheri_capability_set_null(&cfp->cf_c4); + cheri_capability_set_null(&cfp->cf_c5); + cheri_capability_set_null(&cfp->cf_c6); + cheri_capability_set_null(&cfp->cf_c7); + cheri_capability_set_null(&cfp->cf_c8); + cheri_capability_set_null(&cfp->cf_c9); + cheri_capability_set_null(&cfp->cf_c10); + cheri_capability_set_null(&cfp->cf_c11); + cheri_capability_set_null(&cfp->cf_c12); + cheri_capability_set_null(&cfp->cf_c13); + cheri_capability_set_null(&cfp->cf_c14); + cheri_capability_set_null(&cfp->cf_c15); + cheri_capability_set_null(&cfp->cf_c16); + cheri_capability_set_null(&cfp->cf_c17); + cheri_capability_set_null(&cfp->cf_c18); + cheri_capability_set_null(&cfp->cf_c19); + cheri_capability_set_null(&cfp->cf_c20); + cheri_capability_set_null(&cfp->cf_c21); + cheri_capability_set_null(&cfp->cf_c22); + cheri_capability_set_null(&cfp->cf_c23); + cheri_capability_set_null(&cfp->cf_c24); + cheri_capability_set_null(&cfp->cf_c26); /* * XXXRW: not in CHERI ISAv2: - * cp2_capability_set_null(&cfp->cf_tsc); + * cheri_capability_set_null(&cfp->cf_tsc); */ - cp2_capability_set_user(&cfp->cf_pcc); + cheri_capability_set_user(&cfp->cf_pcc); } #ifdef DDB -#define DB_CP2_REG_PRINT_NUM(crn, num) do { \ +#define DB_CHERI_REG_PRINT_NUM(crn, num) do { \ struct chericap c; \ \ CHERI_GETCAPREG((crn), c); \ @@ -249,56 +249,57 @@ (uintmax_t)c.c_length); \ } while (0) -#define DB_CP2_REG_PRINT(crn) DB_CP2_REG_PRINT_NUM(crn, crn) +#define DB_CHERI_REG_PRINT(crn) DB_CHERI_REG_PRINT_NUM(crn, crn) /* - * Variation that prints live register state from CP2. + * Variation that prints live register state from the capability coprocessor. */ -DB_SHOW_COMMAND(cp2, ddb_dump_cp2) +DB_SHOW_COMMAND(cheri, ddb_dump_cheri) { - db_printf("CP2 registers\n"); - DB_CP2_REG_PRINT(0); - DB_CP2_REG_PRINT(1); - DB_CP2_REG_PRINT(2); - DB_CP2_REG_PRINT(3); - DB_CP2_REG_PRINT(4); - DB_CP2_REG_PRINT(5); - DB_CP2_REG_PRINT(6); - DB_CP2_REG_PRINT(7); - DB_CP2_REG_PRINT(8); - DB_CP2_REG_PRINT(9); - DB_CP2_REG_PRINT(10); - DB_CP2_REG_PRINT(11); - DB_CP2_REG_PRINT(12); - DB_CP2_REG_PRINT(13); - DB_CP2_REG_PRINT(14); - DB_CP2_REG_PRINT(15); - DB_CP2_REG_PRINT(16); - DB_CP2_REG_PRINT(17); - DB_CP2_REG_PRINT(18); - DB_CP2_REG_PRINT(19); - DB_CP2_REG_PRINT(20); - DB_CP2_REG_PRINT(21); - DB_CP2_REG_PRINT(22); - DB_CP2_REG_PRINT(23); - DB_CP2_REG_PRINT(24); - DB_CP2_REG_PRINT(25); - DB_CP2_REG_PRINT(26); - DB_CP2_REG_PRINT(27); - DB_CP2_REG_PRINT(28); - DB_CP2_REG_PRINT(29); - DB_CP2_REG_PRINT(30); - DB_CP2_REG_PRINT(31); + db_printf("CHERI registers\n"); + DB_CHERI_REG_PRINT(0); + DB_CHERI_REG_PRINT(1); + DB_CHERI_REG_PRINT(2); + DB_CHERI_REG_PRINT(3); + DB_CHERI_REG_PRINT(4); + DB_CHERI_REG_PRINT(5); + DB_CHERI_REG_PRINT(6); + DB_CHERI_REG_PRINT(7); + DB_CHERI_REG_PRINT(8); + DB_CHERI_REG_PRINT(9); + DB_CHERI_REG_PRINT(10); + DB_CHERI_REG_PRINT(11); + DB_CHERI_REG_PRINT(12); + DB_CHERI_REG_PRINT(13); + DB_CHERI_REG_PRINT(14); + DB_CHERI_REG_PRINT(15); + DB_CHERI_REG_PRINT(16); + DB_CHERI_REG_PRINT(17); + DB_CHERI_REG_PRINT(18); + DB_CHERI_REG_PRINT(19); + DB_CHERI_REG_PRINT(20); + DB_CHERI_REG_PRINT(21); + DB_CHERI_REG_PRINT(22); + DB_CHERI_REG_PRINT(23); + DB_CHERI_REG_PRINT(24); + DB_CHERI_REG_PRINT(25); + DB_CHERI_REG_PRINT(26); + DB_CHERI_REG_PRINT(27); + DB_CHERI_REG_PRINT(28); + DB_CHERI_REG_PRINT(29); + DB_CHERI_REG_PRINT(30); + DB_CHERI_REG_PRINT(31); } /* - * Variation that prints the saved userspace CP2 register frame for a thread. + * Variation that prints the saved userspace CHERI register frame for a + * thread. */ -DB_SHOW_COMMAND(cp2frame, ddb_dump_cp2frame) +DB_SHOW_COMMAND(cheriframe, ddb_dump_cheriframe) { struct thread *td; - struct cp2_frame *cfp; + struct cheri_frame *cfp; register_t s; u_int i; @@ -307,28 +308,28 @@ else td = curthread; - cfp = &td->td_pcb->pcb_cp2frame; + cfp = &td->td_pcb->pcb_cheriframe; db_printf("Thread %d at %p\n", td->td_tid, td); - db_printf("CP2 frame at %p\n", cfp); + db_printf("CHERI frame at %p\n", cfp); /* Laboriously load and print each capability. */ for (i = 0; i < 25; i++) { s = intr_disable(); - cp2_capability_load(CHERI_CR_KR1C, + cheri_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + i); - DB_CP2_REG_PRINT_NUM(CHERI_CR_KR1C, i); + DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, i); intr_restore(s); } db_printf("\nPCC:\n"); s = intr_disable(); #if 0 - cp2_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + + cheri_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + CHERI_CR_TSC_OFF); - DB_CP2_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_TSC); + DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_TSC); #endif - cp2_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + + cheri_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + CHERI_CR_PCC_OFF); - DB_CP2_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_EPCC); + DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_EPCC); intr_restore(s); } #endif ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#9 (text+ko) ==== @@ -66,10 +66,10 @@ * struct mips_frame. As with mips_frame, the order of save/restore is very * important for both reasons of correctness and security. * - * Must match the register offset definitions (CHERI_*_OFF) in cp2reg.h. + * Must match the register offset definitions (CHERI_*_OFF) in cherireg.h. */ #ifdef _KERNEL -struct cp2_frame { +struct cheri_frame { /* c0 has special properties for MIPS load/store instructions. */ struct chericap cf_c0; @@ -78,7 +78,7 @@ * CHERI ISA spec (ISAv2). * * XXXRW: Currently, C25 is used in-kernel to maintain a saved UDC - * (C0), and so not part of cp2_frame. This will change in the + * (C0), and so not part of cheri_frame. This will change in the * future. */ struct chericap cf_c1, cf_c2, cf_c3, cf_c4; @@ -100,7 +100,7 @@ */ struct chericap cf_pcc; }; -CTASSERT(sizeof(struct cp2_frame) == (27 * CHERICAP_SIZE)); +CTASSERT(sizeof(struct cheri_frame) == (27 * CHERICAP_SIZE)); #endif /* @@ -232,14 +232,14 @@ } while (0) static inline void -cp2_capability_load(u_int crn_to, struct chericap *cp) +cheri_capability_load(u_int crn_to, struct chericap *cp) { CHERI_CLC(crn_to, CHERI_CR_KDC, cp, 0); } static inline void -cp2_capability_store(u_int crn_from, struct chericap *cp) +cheri_capability_store(u_int crn_from, struct chericap *cp) { CHERI_CSC(crn_from, CHERI_CR_KDC, cp, 0); @@ -261,19 +261,20 @@ * APIs that act on C language representations of capabilities -- but not * capabilities themselves. */ -void cp2_capability_copy(struct chericap *cp_to, struct chericap *cp_from); -void cp2_capability_set(struct chericap *cp, uint32_t uperms, +void cheri_capability_copy(struct chericap *cp_to, + struct chericap *cp_from); +void cheri_capability_set(struct chericap *cp, uint32_t uperms, void *otypep /* eaddr */, void *basep, uint64_t length); -void cp2_capability_set_priv(struct chericap *cp); -void cp2_capability_set_user(struct chericap *cp); -void cp2_capability_set_null(struct chericap *cp); +void cheri_capability_set_priv(struct chericap *cp); +void cheri_capability_set_user(struct chericap *cp); +void cheri_capability_set_null(struct chericap *cp); #ifdef _KERNEL /* * Kernel-specific CHERI context management functions. */ -void cp2_context_copy(struct cp2_frame *cf_destp, - struct cp2_frame *cf_srcp); +void cheri_context_copy(struct cheri_frame *cf_destp, + struct cheri_frame *cf_srcp); void cheri_exec_setregs(struct thread *td); #endif ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#8 (text+ko) ==== @@ -78,90 +78,86 @@ 66: /* - * Macros to save and restore CP2 registers from pcb.pcb_cp2frame, - * individually and in quantity. Explicitly use $kdc ($30), which - * U_PCB_CP2FRAME is assumed to be valid for, but that the userspace $c0 has - * been set aside in $sc0 ($c25). This assumes previous or further calls to - * CHERI_EXECPTION_ENTER() and CHERI_EXCEPTION_RETURN() to manage $c0. - * - * XXXRW: Here, it would be nice if CSCR and CLCR took immediate offsets, not - * just a register offset so that we could avoid using treg. + * Macros to save and restore CHERI capability registers registers from + * pcb.pcb_cheriframe, individually and in quantity. Explicitly use $kdc + * ($30), which U_PCB_CHERIFRAME is assumed to be valid for, but that the + * userspace $c0 has been set aside in $sc0 ($c25). This assumes previous or + * further calls to CHERI_EXECPTION_ENTER() and CHERI_EXCEPTION_RETURN() to + * manage $c0. */ #define SZCAP 32 -#define SAVE_U_PCB_CP2REG(treg, creg, offs, base) \ - daddu treg, base, U_PCB_CP2FRAME + (SZCAP * offs); \ - cscr creg, treg($c30) +#define SAVE_U_PCB_CHERIREG(creg, offs, base) \ + csc creg, base, (U_PCB_CHERIFRAME + (SZCAP * offs))($c30) -#define RESTORE_U_PCB_CP2REG(treg, creg, offs, base) \ - daddu treg, base, U_PCB_CP2FRAME + (SZCAP * offs); \ - clcr creg, treg($c30) +#define RESTORE_U_PCB_CHERIREG(creg, offs, base) \ + clc creg, base, (U_PCB_CHERIFRAME + (SZCAP * offs))($c30) /* - * XXXRW: Update once the assembler supports reserved CP2 register names to + * XXXRW: Update once the assembler supports reserved CHERI register names to * avoid hard-coding here. * - * XXXRW: It woudld be nice to make calls to these conditional on actual CP2 + * XXXRW: It woudld be nice to make calls to these conditional on actual CHERI * coprocessor use, similar to on-demand context management for other MIPS * coprocessors (e.g., FP). * * XXXRW: Note hard-coding of UDC here. */ -#define SAVE_CP2_CONTEXT(treg, base) \ - SAVE_U_PCB_CP2REG(treg, $c25, CHERI_CR_C0_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c1, CHERI_CR_C1_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c2, CHERI_CR_C2_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c3, CHERI_CR_C3_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c4, CHERI_CR_C4_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c5, CHERI_CR_C5_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c6, CHERI_CR_C6_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c7, CHERI_CR_C7_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c8, CHERI_CR_C8_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c9, CHERI_CR_C9_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c10, CHERI_CR_C10_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c11, CHERI_CR_C11_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c12, CHERI_CR_C12_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c13, CHERI_CR_C13_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c14, CHERI_CR_C14_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c15, CHERI_CR_C15_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c16, CHERI_CR_C16_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c17, CHERI_CR_C17_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c18, CHERI_CR_C18_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c19, CHERI_CR_C19_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c20, CHERI_CR_C20_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c21, CHERI_CR_C21_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c22, CHERI_CR_C22_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c23, CHERI_CR_C23_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c24, CHERI_CR_C24_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c26, CHERI_CR_C26_OFF, base); \ - SAVE_U_PCB_CP2REG(treg, $c31, CHERI_CR_PCC_OFF, base) +#define SAVE_CHERI_CONTEXT(base) \ + SAVE_U_PCB_CHERIREG($c25, CHERI_CR_C0_OFF, base); \ + SAVE_U_PCB_CHERIREG($c1, CHERI_CR_C1_OFF, base); \ + SAVE_U_PCB_CHERIREG($c2, CHERI_CR_C2_OFF, base); \ + SAVE_U_PCB_CHERIREG($c3, CHERI_CR_C3_OFF, base); \ + SAVE_U_PCB_CHERIREG($c4, CHERI_CR_C4_OFF, base); \ + SAVE_U_PCB_CHERIREG($c5, CHERI_CR_C5_OFF, base); \ + SAVE_U_PCB_CHERIREG($c6, CHERI_CR_C6_OFF, base); \ + SAVE_U_PCB_CHERIREG($c7, CHERI_CR_C7_OFF, base); \ + SAVE_U_PCB_CHERIREG($c8, CHERI_CR_C8_OFF, base); \ + SAVE_U_PCB_CHERIREG($c9, CHERI_CR_C9_OFF, base); \ + SAVE_U_PCB_CHERIREG($c10, CHERI_CR_C10_OFF, base); \ + SAVE_U_PCB_CHERIREG($c11, CHERI_CR_C11_OFF, base); \ + SAVE_U_PCB_CHERIREG($c12, CHERI_CR_C12_OFF, base); \ + SAVE_U_PCB_CHERIREG($c13, CHERI_CR_C13_OFF, base); \ + SAVE_U_PCB_CHERIREG($c14, CHERI_CR_C14_OFF, base); \ + SAVE_U_PCB_CHERIREG($c15, CHERI_CR_C15_OFF, base); \ + SAVE_U_PCB_CHERIREG($c16, CHERI_CR_C16_OFF, base); \ + SAVE_U_PCB_CHERIREG($c17, CHERI_CR_C17_OFF, base); \ + SAVE_U_PCB_CHERIREG($c18, CHERI_CR_C18_OFF, base); \ + SAVE_U_PCB_CHERIREG($c19, CHERI_CR_C19_OFF, base); \ + SAVE_U_PCB_CHERIREG($c20, CHERI_CR_C20_OFF, base); \ + SAVE_U_PCB_CHERIREG($c21, CHERI_CR_C21_OFF, base); \ + SAVE_U_PCB_CHERIREG($c22, CHERI_CR_C22_OFF, base); \ + SAVE_U_PCB_CHERIREG($c23, CHERI_CR_C23_OFF, base); \ + SAVE_U_PCB_CHERIREG($c24, CHERI_CR_C24_OFF, base); \ + SAVE_U_PCB_CHERIREG($c26, CHERI_CR_C26_OFF, base); \ + SAVE_U_PCB_CHERIREG($c31, CHERI_CR_PCC_OFF, base) -#define RESTORE_CP2_CONTEXT(treg, base) \ - RESTORE_U_PCB_CP2REG(treg, $c25, CHERI_CR_C0_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c1, CHERI_CR_C1_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c2, CHERI_CR_C2_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c3, CHERI_CR_C3_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c4, CHERI_CR_C4_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c5, CHERI_CR_C5_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c6, CHERI_CR_C6_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c7, CHERI_CR_C7_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c8, CHERI_CR_C8_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c9, CHERI_CR_C9_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c10, CHERI_CR_C10_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c11, CHERI_CR_C11_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c12, CHERI_CR_C12_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c13, CHERI_CR_C13_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c14, CHERI_CR_C14_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c15, CHERI_CR_C15_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c16, CHERI_CR_C16_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c17, CHERI_CR_C17_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c18, CHERI_CR_C18_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c19, CHERI_CR_C19_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c20, CHERI_CR_C20_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c21, CHERI_CR_C21_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c22, CHERI_CR_C22_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c23, CHERI_CR_C23_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c24, CHERI_CR_C24_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c26, CHERI_CR_C26_OFF, base); \ - RESTORE_U_PCB_CP2REG(treg, $c31, CHERI_CR_PCC_OFF, base) +#define RESTORE_CHERI_CONTEXT(base) \ + RESTORE_U_PCB_CHERIREG($c25, CHERI_CR_C0_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c1, CHERI_CR_C1_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c2, CHERI_CR_C2_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c3, CHERI_CR_C3_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c4, CHERI_CR_C4_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c5, CHERI_CR_C5_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c6, CHERI_CR_C6_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c7, CHERI_CR_C7_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c8, CHERI_CR_C8_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c9, CHERI_CR_C9_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c10, CHERI_CR_C10_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c11, CHERI_CR_C11_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c12, CHERI_CR_C12_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c13, CHERI_CR_C13_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c14, CHERI_CR_C14_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c15, CHERI_CR_C15_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c16, CHERI_CR_C16_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c17, CHERI_CR_C17_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c18, CHERI_CR_C18_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c19, CHERI_CR_C19_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c20, CHERI_CR_C20_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c21, CHERI_CR_C21_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c22, CHERI_CR_C22_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c23, CHERI_CR_C23_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c24, CHERI_CR_C24_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c26, CHERI_CR_C26_OFF, base); \ + RESTORE_U_PCB_CHERIREG($c31, CHERI_CR_PCC_OFF, base) #endif /* _MIPS_INCLUDE_CHERIASM_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#7 (text+ko) ==== @@ -152,7 +152,7 @@ #define CHERI_CR_EPCC CHERI_CR_C31 /* Exception program counter cap. */ /* - * Offsets of registers in struct cp2_frame -- must match the definition in + * Offsets of registers in struct cheri_frame -- must match the definition in * cheri.h. */ #define CHERI_CR_C0_OFF 0 ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/pcb.h#6 (text+ko) ==== @@ -55,7 +55,7 @@ { struct trapframe pcb_regs; /* saved CPU and registers */ #ifdef CPU_CHERI - struct cp2_frame pcb_cp2frame; /* Userspace capabilities. */ + struct cheri_frame pcb_cheriframe; /* Userspace capabilities. */ #endif __register_t pcb_context[14]; /* kernel context for resume */ void *pcb_onfault; /* for copyin/copyout faults */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/exception.S#10 (text+ko) ==== @@ -505,7 +505,7 @@ /* * Note: This saves EPCC, matching the explicit EPC save above. */ - SAVE_CP2_CONTEXT(t0, k1) + SAVE_CHERI_CONTEXT(k1) #endif REG_S a3, CALLFRAME_RA(sp) # for debugging PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP @@ -560,7 +560,7 @@ /* * Note: This restores EPCC, matching the explicit EPC restore below. */ - RESTORE_CP2_CONTEXT(t0, k1) + RESTORE_CHERI_CONTEXT(k1) #endif RESTORE_U_PCB_REG(t0, MULLO, k1) RESTORE_U_PCB_REG(t1, MULHI, k1) @@ -662,10 +662,10 @@ /* * Check for getting interrupts just before wait * - * XXXCHERI: Once we use variable CP2 PCC in the kernel, this check will also - * need to take that into account. In the mean time, the fact that we're in - * the kernel ring is sufficient to imply that PCC matches the kernel address - * space. + * XXXCHERI: Once we use variable CHERI PCC in the kernel, this check will + * also need to take that into account. In the mean time, the fact that we're + * in the kernel ring is sufficient to imply that PCC matches the kernel + * address space. */ MFC0 k0, MIPS_COP_0_EXC_PC ori k0, 0xf @@ -786,7 +786,7 @@ /* * Note: This saves EPCC, matching the explicit EPC save above. */ - SAVE_CP2_CONTEXT(t0, k1) + SAVE_CHERI_CONTEXT(k1) #endif PTR_SUBU sp, k1, CALLFRAME_SIZ # switch to kernel SP PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP @@ -850,7 +850,7 @@ /* * Note: This restores EPCC, matching the explicit EPC restore below. */ - RESTORE_CP2_CONTEXT(t0, k1) + RESTORE_CHERI_CONTEXT(k1) #endif RESTORE_U_PCB_REG(s0, S0, k1) RESTORE_U_PCB_REG(s1, S1, k1) @@ -1056,8 +1056,8 @@ /* * XXXCHERI: This SAVE_CPU preserves a kernel register frame before * entering the kernel debugger on kernel stack overflow. In the - * future, we may want to do something with CP2 EPCC here (e.g., save - * it?). + * future, we may want to do something with CHERI EPCC here (e.g., + * save it?). */ SAVE_CPU ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/genassym.c#4 (text+ko) ==== @@ -75,7 +75,7 @@ ASSYM(U_PCB_REGS, offsetof(struct pcb, pcb_regs.zero)); #ifdef CPU_CHERI -ASSYM(U_PCB_CP2FRAME, offsetof(struct pcb, pcb_cp2frame.cf_c0)); +ASSYM(U_PCB_CHERIFRAME, offsetof(struct pcb, pcb_cheriframe.cf_c0)); #endif ASSYM(U_PCB_CONTEXT, offsetof(struct pcb, pcb_context)); ASSYM(U_PCB_ONFAULT, offsetof(struct pcb, pcb_onfault)); ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/swtch.S#9 (text+ko) ==== @@ -124,7 +124,7 @@ /* * Note: This restores EPCC, matching the explicit EPC restore below. */ - RESTORE_CP2_CONTEXT(t0, k1) + RESTORE_CHERI_CONTEXT(k1) #endif RESTORE_U_PCB_REG(t0, MULLO, k1) RESTORE_U_PCB_REG(t1, MULHI, k1) @@ -264,7 +264,7 @@ SAVE_U_PCB_CONTEXT(ra, PREG_PC, a0) # save return address #ifdef CPU_CHERI - /* XXXRW: CP2 state management here. */ + /* XXXRW: CHERI state management here. */ #endif #ifdef CPU_CNMIPS