Date: Sat, 1 Oct 2016 03:35:03 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r306550 - head/sys/arm/nvidia/tegra124 Message-ID: <201610010335.u913Z3iK085018@repo.freebsd.org>
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Author: mmel Date: Sat Oct 1 03:35:03 2016 New Revision: 306550 URL: https://svnweb.freebsd.org/changeset/base/306550 Log: TEGRA: Extend timeout for PLLs lock to 5 ms. Real lock time for PLLA has been very near to old limit. Modified: head/sys/arm/nvidia/tegra124/tegra124_clk_pll.c Modified: head/sys/arm/nvidia/tegra124/tegra124_clk_pll.c ============================================================================== --- head/sys/arm/nvidia/tegra124/tegra124_clk_pll.c Sat Oct 1 03:24:53 2016 (r306549) +++ head/sys/arm/nvidia/tegra124/tegra124_clk_pll.c Sat Oct 1 03:35:03 2016 (r306550) @@ -86,7 +86,7 @@ enum pll_type { #define PLLRE_IDDQ_BIT 16 #define PLLSS_IDDQ_BIT 19 -#define PLL_LOCK_TIMEOUT 1000 +#define PLL_LOCK_TIMEOUT 5000 /* Post divider <-> register value mapping. */ struct pdiv_table {
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