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Date: Thu, 17 Aug 1995 10:56:34 -0400 (EDT)
From: "Jonathan M. Bresler" <jmb@kryten.Atinc.COM>
Subject: Re: i82424ZX vs i82424TX cache dram controller
To: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com>
cc: freebsd-hardware@freebsd.org
In-Reply-To: <199508170102.SAA21491@gndrsh.aac.dev.com>
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On Wed, 16 Aug 1995, Rodney W. Grimes wrote:

> > ps.  the asus sp3g uses:
> > 	chip0 <intel 82424ZX cache dram controller> on pci0:0
> > 	chip1 <intel 82378IB pci-isa bridge> on pci0:2
> 
> You left out a bit of that string, and it is an important part:
> chip0 <Intel 82424ZX cache DRAM controller> rev 4 on pci0:0
>                                             ^^^^^
> As far as I can assertain rev 0, 1 and 2 are Saturn I, 3 and 4
> are Saturn II.  Since Intel data books do not publish code names,
> it is very hard to figure these things out at times :-(.

	hmm...looking into pcisupport.c, i see that most printf()'s are 
#ifdef'ed PROBE_VERBOSE.  with PROBE_VERBOSE defined i get:

pci0: scanning device 0..15, mechanism=2.
chip0 <intel 82424ZX cache dram controller> on pci0:0
        CPU: 486DX2 or 486DX4, bus=33MHz, CPU->Memory posting ON
        Warning: NO DRAM parity!
        Cache: 256KB writethrough, cache clocks=2-1-1-1
        DRAM: page mode code fetch, read and write, memory clocks=X-1-2-1
        CPU->PCI: posting ON, burst mode OFF
        PCI->Memory: posting ON
[snip]
chip1 <intel 82378IB pci-isa bridge> on pci0:2
        [40] 41e23 [50] 0 [54] 4000000


	still no rev message--from looking at source that seems to be in 
-current and 2.0.5R but not in 2.0R
	
jmb

Jonathan M. Bresler  jmb@kryten.atinc.com       | Analysis & Technology, Inc.  
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