Date: Wed, 04 Apr 2018 10:09:57 +0000 From: bugzilla-noreply@freebsd.org To: freebsd-ports-bugs@FreeBSD.org Subject: [Bug 227254] [New Port] devel/abc: System for Sequential Synthesis and Verification Message-ID: <bug-227254-13-WRZ4h8i6rO@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-227254-13@https.bugs.freebsd.org/bugzilla/> References: <bug-227254-13@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D227254 --- Comment #2 from Christian Kr=C3=A4mer <uddka@student.kit.edu> --- (In reply to Yuri Victorovich from comment #1) You are right. On second thought, cad seems more suitable... --=20 You are receiving this mail because: You are the assignee for the bug.=
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