From owner-svn-src-stable-7@FreeBSD.ORG Fri Sep 25 17:07:44 2009 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 411D31065676; Fri, 25 Sep 2009 17:07:44 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 2F6AA8FC12; Fri, 25 Sep 2009 17:07:44 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n8PH7iXi034477; Fri, 25 Sep 2009 17:07:44 GMT (envelope-from marius@svn.freebsd.org) Received: (from marius@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n8PH7iJu034475; Fri, 25 Sep 2009 17:07:44 GMT (envelope-from marius@svn.freebsd.org) Message-Id: <200909251707.n8PH7iJu034475@svn.freebsd.org> From: Marius Strobl Date: Fri, 25 Sep 2009 17:07:44 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r197489 - in stable/7/sys: . contrib/pf dev/ata X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Sep 2009 17:07:44 -0000 Author: marius Date: Fri Sep 25 17:07:43 2009 New Revision: 197489 URL: http://svn.freebsd.org/changeset/base/197489 Log: MFC: 197402 - Add missing bus_dmamap_sync(9) calls for the work DMA map. Previously the work area was totally unsynchronized which means this driver only had a chance of working on x86 when no bounce buffers were involved, which isn't that likely given that support for 64-bit DMA is currently broken throughout ata(4). - Add necessary little-endian conversion of accesses to the work area, making this driver work on big-endian hosts. While at it, use the alignment-agnostic byte order encoders in order to be on the safe side. - Clear the reserved member of the SG list entries in order to be on the safe side. [1] Submitted by: yongari [1] Reviewed by: yongari Modified: stable/7/sys/ (props changed) stable/7/sys/contrib/pf/ (props changed) stable/7/sys/dev/ata/ata-chipset.c Modified: stable/7/sys/dev/ata/ata-chipset.c ============================================================================== --- stable/7/sys/dev/ata/ata-chipset.c Fri Sep 25 16:45:27 2009 (r197488) +++ stable/7/sys/dev/ata/ata-chipset.c Fri Sep 25 17:07:43 2009 (r197489) @@ -2690,6 +2690,8 @@ ata_marvell_edma_allocate(device_t dev) /* clear work area */ bzero(ch->dma->work, 1024+256); + bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* set legacy ATA resources */ for (i = ATA_DATA; i <= ATA_COMMAND; i++) { @@ -2799,8 +2801,6 @@ ata_marvell_edma_begin_transaction(struc struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); u_int32_t req_in; u_int8_t *bytep; - u_int16_t *wordp; - u_int32_t *quadp; int i, tag = 0x07; int dummy, error, slot; @@ -2831,13 +2831,14 @@ ata_marvell_edma_begin_transaction(struc slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; bytep = (u_int8_t *)(ch->dma->work); bytep += (slot << 5); - wordp = (u_int16_t *)bytep; - quadp = (u_int32_t *)bytep; /* fill in this request */ - quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; - quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; - wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); + le32enc(bytep + 0 * sizeof(u_int32_t), + ch->dma->sg_bus & 0xffffffff); + le32enc(bytep + 1 * sizeof(u_int32_t), + (u_int64_t)ch->dma->sg_bus >> 32); + le16enc(bytep + 4 * sizeof(u_int16_t), + (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag << 1)); i = 10; bytep[i++] = (request->u.ata.count >> 8) & 0xff; @@ -2866,6 +2867,9 @@ ata_marvell_edma_begin_transaction(struc bytep[i++] = request->u.ata.command; bytep[i++] = 0x90 | ATA_COMMAND; + bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* enable EDMA machinery if needed */ if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); @@ -2908,6 +2912,8 @@ ata_marvell_edma_end_transaction(struct slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; rsp_out &= 0xffffff00; rsp_out += (slot << 3); + bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); response = (struct ata_marvell_response *) (ch->dma->work + 1024 + (slot << 3)); @@ -2982,6 +2988,7 @@ ata_marvell_edma_dmasetprd(void *xsc, bu prd[i].addrlo = htole32(segs[i].ds_addr); prd[i].count = htole32(segs[i].ds_len); prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); + prd[i].reserved = 0; } prd[i - 1].count |= htole32(ATA_DMA_EOT); KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));