Date: Fri, 22 Feb 2008 16:51:35 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 135967 for review Message-ID: <200802221651.m1MGpZ3Y029943@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=135967 Change 135967 by imp@imp_lighthouse on 2008/02/22 16:50:58 Harmonize the tick init stuff to be the same on all platforms. Remove prototypes that should be in header files and move relevant ones there. Expand the early_init clock frequency to be 64 bits. This gets both octeon and malta compiling again. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/conf/files.mips#16 edit .. //depot/projects/mips2-jnpr/src/sys/mips/include/clock.h#8 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#7 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#16 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/conf/files.mips#16 (text+ko) ==== @@ -55,7 +55,7 @@ # Phase 4 # ---------------------------------------------------------------------- # -#mips/mips/clock.c standard +mips/mips/tick.c standard #mips/mips/queue.c standard # ---------------------------------------------------------------------- # Phase 5 ==== //depot/projects/mips2-jnpr/src/sys/mips/include/clock.h#8 (text+ko) ==== @@ -28,6 +28,7 @@ */ #define MIPS_DEFAULT_HZ (100 * 1000 * 1000) +void mips_timer_early_init(uint64_t clock_hz); void mips_timer_init_params(uint64_t, int); int sysbeep(int pitch, int period); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#7 (text+ko) ==== @@ -59,7 +59,8 @@ u_int32_t counter_lower_last = 0; int tick_started = 0; -struct clk_ticks { +struct clk_ticks +{ u_long hard_ticks; u_long stat_ticks; u_long prof_ticks; @@ -81,19 +82,16 @@ static struct timecounter counter_timecounter = { counter_get_timecount, /* get_timecount */ 0, /* no poll_pps */ - ~0u, /* counter_mask */ + 0xffffffffu, /* counter_mask */ 0, /* frequency */ "MIPS32", /* name */ 800, /* quality (adjusted in code) */ }; -void tick_early_init(uint32_t); -void tick_init_params(uint64_t, int ); - void -tick_early_init(uint32_t clock_hz) +mips_timer_early_init(uint64_t clock_hz) { - /* Cavium early init code */ + /* Initialize clock early so that we can use DELAY sooner */ counter_freq = clock_hz; cycles_per_usec = (clock_hz / (1000 * 1000)); } @@ -108,19 +106,22 @@ } } - - static uint64_t tick_ticker(void) { uint64_t ret; uint32_t ticktock; + /* + * XXX: MIPS64 platforms can read 64-bits of counter directly. + * Also: the tc code is supposed to cope with things wrapping + * from the time counter, so I'm not sure why all these hoops + * are even necessary. + */ ticktock = mips_rd_count(); critical_enter(); - if (ticktock < counter_lower_last) { + if (ticktock < counter_lower_last) counter_upper++; - } counter_lower_last = ticktock; critical_exit(); @@ -128,10 +129,8 @@ return (ret); } - - void -tick_init_params(uint64_t platform_counter_freq, int double_count) +mips_timer_init_params(uint64_t platform_counter_freq, int double_count) { /* @@ -139,21 +138,18 @@ * function should be called before cninit. */ counter_freq = platform_counter_freq; - cycles_per_tick = counter_freq / 1000; - if(double_count) - cycles_per_tick *=2; - + if (double_count) + cycles_per_tick *= 2; cycles_per_hz = counter_freq / hz; - cycles_per_usec = counter_freq / (1 * 1000 * 1000); - cycles_per_sec = counter_freq / (1 * 1000); - counter_timecounter.tc_frequency = counter_freq; /* * XXX: Some MIPS32 cores update the Count register only every two * pipeline cycles. + * XXX2: We can read this from the hardware register on some + * systems. Need to investigate. */ if (double_count != 0) { cycles_per_hz /= 2; ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#16 (text+ko) ==== @@ -1313,9 +1313,6 @@ } -void tick_early_init(uint32_t clock_hz); -void tick_init_params(uint64_t platform_counter_freq, int double_count); - void platform_start(__register_t a0 __unused, __register_t a1 __unused, __register_t a2 __unused, __register_t a3 __unused) @@ -1328,17 +1325,16 @@ /* The boot loader clears the BSS and SBSS segments */ kernend = round_page((vm_offset_t)&end); - tick_early_init(OCTEON_CLOCK_DEFAULT); /* Quick Default. To avoid - * divide-by-0 Later we will - * get it from - * Bootloader/Rom-Mon */ - + /* + * Quick Default. To avoid divide-by-0 Later we will + * get it from Bootloader/Rom-Mon + */ + mips_timer_early_init(OCTEON_CLOCK_DEFAULT); cninit(); mips_boot_params_init(); printf(" Initialized memory: 0x%p to 0x%lX\n", &edata, ((long)&edata) + ((long)kernend - (long)(&edata))); mips_init(); platform_counter_freq = (uint64_t) (octeon_get_clock_rate()); - - tick_init_params(platform_counter_freq, 0); + mips_timer_init_params(platform_counter_freq, 0); }
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