From owner-cvs-src@FreeBSD.ORG Mon Jul 30 22:29:35 2007 Return-Path: Delivered-To: cvs-src@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 7994F16A41A; Mon, 30 Jul 2007 22:29:35 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 7121813C45B; Mon, 30 Jul 2007 22:29:35 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id l6UMTZN8024295; Mon, 30 Jul 2007 22:29:35 GMT (envelope-from marcel@repoman.freebsd.org) Received: (from marcel@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id l6UMTZWO024294; Mon, 30 Jul 2007 22:29:35 GMT (envelope-from marcel) Message-Id: <200707302229.l6UMTZWO024294@repoman.freebsd.org> From: Marcel Moolenaar Date: Mon, 30 Jul 2007 22:29:33 +0000 (UTC) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: src/sys/ia64/ia64 interrupt.c nexus.c sapic.c src/sys/ia64/include intr.h md_var.h sapicvar.h X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jul 2007 22:29:35 -0000 marcel 2007-07-30 22:29:33 UTC FreeBSD src repository Modified files: sys/ia64/ia64 interrupt.c nexus.c sapic.c sys/ia64/include intr.h md_var.h sapicvar.h Log: Rework the interrupt code and add support for interrupt filtering (INTR_FILTER). This includes: o Save a pointer to the sapic structure and IRQ for every vector, so that we can quickly EOI, mask and unmask the interrupt. o Add locking to the sapic code now that we can reprogram a sapic on multiple CPUs at the same time. o Use u_int for the vector and IRQ. We only have 256 vectors, so using a 64-bit type for it is rather excessive. o Properly handle concurrent registration of a handler for the same vector. Since vectors have a corresponding priority, we should not map IRQs to vectors in a linear fashion, but rather pick a vector that has a priority in line with the interrupt type. This is left for later. The vector/IRQ interchange has been untangled as much as possible to make this easier. Approved by: re (blacket) Revision Changes Path 1.60 +114 -81 src/sys/ia64/ia64/interrupt.c 1.18 +1 -1 src/sys/ia64/ia64/nexus.c 1.14 +109 -80 src/sys/ia64/ia64/sapic.c 1.5 +1 -6 src/sys/ia64/include/intr.h 1.25 +1 -1 src/sys/ia64/include/md_var.h 1.5 +13 -8 src/sys/ia64/include/sapicvar.h