From owner-svn-src-stable-8@FreeBSD.ORG Tue Nov 16 20:32:09 2010 Return-Path: Delivered-To: svn-src-stable-8@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id F03C310656A7; Tue, 16 Nov 2010 20:32:09 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id C39DA8FC1A; Tue, 16 Nov 2010 20:32:09 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oAGKW9YK066537; Tue, 16 Nov 2010 20:32:09 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oAGKW98l066534; Tue, 16 Nov 2010 20:32:09 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201011162032.oAGKW98l066534@svn.freebsd.org> From: Pyun YongHyeon Date: Tue, 16 Nov 2010 20:32:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r215405 - in stable/8/sys: dev/re pci X-BeenThere: svn-src-stable-8@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 8-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Nov 2010 20:32:10 -0000 Author: yongari Date: Tue Nov 16 20:32:09 2010 New Revision: 215405 URL: http://svn.freebsd.org/changeset/base/215405 Log: MFC r215017,215025: Follow the lead of vendor's interrupt moderation mechanism. It seems RTL8169/RTL8168/RTL810xE has a kind of interrupt moderation mechanism but it is not documented at all. The magic value dramatically reduced number of interrupts without noticeable performance drops so apply it to all RTL8169/RTL8169 controllers. Vendor's FreeBSD driver also applies it to RTL810xE controllers but their Linux driver explicitly cleared the register, so do not enable interrupt moderation for RTL810xE controllers. While I'm here sort 8169 specific registers. Obtained from: RealTek FreeBSD driver MFC r215025: Only moderate TX completion interrupts. Relying on taskqueue to suppress RX interrupts seems to give better RX performance than RX interrupt moderation. Modified: stable/8/sys/dev/re/if_re.c stable/8/sys/pci/if_rlreg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/re/if_re.c ============================================================================== --- stable/8/sys/dev/re/if_re.c Tue Nov 16 20:27:01 2010 (r215404) +++ stable/8/sys/dev/re/if_re.c Tue Nov 16 20:32:09 2010 (r215405) @@ -2715,6 +2715,24 @@ re_init_locked(struct rl_softc *sc) */ re_set_rxmode(sc); + /* Configure interrupt moderation. */ + if (sc->rl_type == RL_8169) { + switch (sc->rl_hwrev) { + case RL_HWREV_8100E: + case RL_HWREV_8101E: + case RL_HWREV_8102E: + case RL_HWREV_8102EL: + case RL_HWREV_8102EL_SPIN1: + case RL_HWREV_8103E: + CSR_WRITE_2(sc, RL_INTRMOD, 0); + break; + default: + /* Magic from vendor. */ + CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); + break; + } + } + #ifdef DEVICE_POLLING /* * Disable interrupts if we are polling. Modified: stable/8/sys/pci/if_rlreg.h ============================================================================== --- stable/8/sys/pci/if_rlreg.h Tue Nov 16 20:27:01 2010 (r215404) +++ stable/8/sys/pci/if_rlreg.h Tue Nov 16 20:32:09 2010 (r215405) @@ -125,6 +125,7 @@ /* * Registers specific to the 8169 gigE chip */ +#define RL_GTXSTART 0x0038 /* 8 bits */ #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ #define RL_PHYAR 0x0060 #define RL_TBICSR 0x0064 @@ -135,7 +136,7 @@ #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ #define RL_PMCH 0x006F /* 8 bits */ #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ -#define RL_GTXSTART 0x0038 /* 8 bits */ +#define RL_INTRMOD 0x00E2 /* 16 bits */ /* * TX config register bits