Date: Sat, 29 Aug 2020 23:43:00 -0700 From: Doug Hardie <bc979@lafn.org> To: Valeri Galtsev <galtsev@kicp.uchicago.edu> Cc: User Questions <freebsd-questions@freebsd.org> Subject: Re: (very OT) Ideal partition schemes (history of partitioning) Message-ID: <BB009B4D-C012-4266-AD26-1E73C012F175@mail.sermon-archive.info> In-Reply-To: <DE243AE0-E6CC-417C-B255-C895705A4DB5@kicp.uchicago.edu> References: <CAGBxaXkf53K4EHtq9cDaRm3MOZZixyBq-aQfZ7upHo-wUwrmCg@mail.gmail.com> <20200829154417.8dd5f83d.freebsd@edvax.de> <alpine.BSF.2.20.2008291356260.79589@fledge.watson.org> <c8440d63-d5d7-3880-d335-a832cfdde55e@kicp.uchicago.edu> <de560479619eba5f3a62e95faaed6323ac2a0e47.camel@riseup.net> <DE243AE0-E6CC-417C-B255-C895705A4DB5@kicp.uchicago.edu>
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-- Doug > On 29 August 2020, at 20:00, Valeri Galtsev = <galtsev@kicp.uchicago.edu> wrote: >=20 >=20 >=20 >=20 > I really hope, someone mentions other machines with 3 address command = system, I really would like to know if the existed. Except BESM-6 which = was built of bipolar transistor blocks, and it predecessor BESM-4 build = on vacuum tubes. >=20 According to Wikipedia: Due to the large number of bits needed to encode the three registers of = a 3-operand instruction, RISC architectures that have 16-bit = instructions are invariably 2-operand designs, such as the Atmel AVR, TI = MSP430, and some versions of ARM Thumb. RISC architectures that have = 32-bit instructions are usually 3-operand designs, such as the ARM, = AVR32, MIPS, Power ISA, and SPARC architectures. I have no experience with any of those. -- Doug
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