Date: Wed, 5 Jul 2006 23:25:17 GMT From: Olivier Houchard <cognet@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 100668 for review Message-ID: <200607052325.k65NPHbf082453@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=100668 Change 100668 by cognet@cognet on 2006/07/05 23:24:19 Override the i386ish specialreg.h with NetBSD's cpuregs.h Affected files ... .. //depot/projects/mips2/src/sys/mips/include/specialreg.h#2 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/include/specialreg.h#2 (text+ko) ==== @@ -1,6 +1,11 @@ -/*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. +/* $NetBSD: cpuregs.h,v 1.69 2005/12/20 21:06:43 tron Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell and Rick Macklem. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -10,7 +15,7 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors + * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * @@ -26,361 +31,781 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 - * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.33 2006/05/01 22:07:00 jhb Exp $ + * @(#)machConst.h 8.1 (Berkeley) 6/10/93 + * + * machConst.h -- + * + * Machine dependent constants. + * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, + * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, + * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, + * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) + */ + +#ifndef _MACHINE_CPUREGS_H_ +#define _MACHINE_CPUREGS_H_ + +#include <sys/cdefs.h> /* For __CONCAT() */ + +/* + * Address space. + * 32-bit mips CPUS partition their 32-bit address space into four segments: + * + * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped + * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped + * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped + * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped + * + * mips1 physical memory is limited to 512Mbytes, which is + * doubly mapped in kseg0 (cached) and kseg1 (uncached.) + * Caching of mapped addresses is controlled by bits in the TLB entry. */ -#ifndef _MACHINE_SPECIALREG_H_ -#define _MACHINE_SPECIALREG_H_ +#define MIPS_KUSEG_START 0x0 +#define MIPS_KSEG0_START 0x80000000 +#define MIPS_KSEG1_START 0xa0000000 +#define MIPS_KSEG2_START 0xc0000000 +#define MIPS_MAX_MEM_ADDR 0xbe000000 +#define MIPS_RESERVED_ADDR 0xbfc80000 + +#define MIPS_PHYS_MASK 0x1fffffff + +#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) +#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) +#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) +#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) + +/* Map virtual address to index in mips3 r4k virtually-indexed cache */ +#define MIPS3_VA_TO_CINDEX(x) \ + ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) + +#define MIPS_PHYS_TO_XKPHYS(cca,x) \ + ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) +#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) + +/* CPU dependent mtc0 hazard hook */ +#define COP0_SYNC /* nothing */ +#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; /* - * Bits in 386 special registers: + * The bits in the cause register. + * + * Bits common to r3000 and r4000: + * + * MIPS_CR_BR_DELAY Exception happened in branch delay slot. + * MIPS_CR_COP_ERR Coprocessor error. + * MIPS_CR_IP Interrupt pending bits defined below. + * (same meaning as in CAUSE register). + * MIPS_CR_EXC_CODE The exception type (see exception codes below). + * + * Differences: + * r3k has 4 bits of execption type, r4k has 5 bits. */ -#define CR0_PE 0x00000001 /* Protected mode Enable */ -#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ -#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ -#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ -#define CR0_PG 0x80000000 /* PaGing enable */ +#define MIPS_CR_BR_DELAY 0x80000000 +#define MIPS_CR_COP_ERR 0x30000000 +#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ +#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ +#define MIPS_CR_IP 0x0000FF00 +#define MIPS_CR_EXC_CODE_SHIFT 2 /* - * Bits in 486 special registers: + * The bits in the status register. All bits are active when set to 1. + * + * R3000 status register fields: + * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. + * MIPS_SR_TS TLB shutdown. + * + * MIPS_SR_INT_IE Master (current) interrupt enable bit. + * + * Differences: + * r3k has cache control is via frobbing SR register bits, whereas the + * r4k cache control is via explicit instructions. + * r3k has a 3-entry stack of kernel/user bits, whereas the + * r4k has kernel/supervisor/user. */ -#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ -#define CR0_WP 0x00010000 /* Write Protect (honor page protect in - all modes) */ -#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ -#define CR0_NW 0x20000000 /* Not Write-through */ -#define CR0_CD 0x40000000 /* Cache Disable */ +#define MIPS_SR_COP_USABILITY 0xf0000000 +#define MIPS_SR_COP_0_BIT 0x10000000 +#define MIPS_SR_COP_1_BIT 0x20000000 + + /* r4k and r3k differences, see below */ + +#define MIPS_SR_MX 0x01000000 /* MIPS64 */ +#define MIPS_SR_PX 0x00800000 /* MIPS64 */ +#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ +#define MIPS_SR_TS 0x00200000 + + /* r4k and r3k differences, see below */ + +#define MIPS_SR_INT_IE 0x00000001 +/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ +/*#define MIPS_SR_INT_MASK 0x0000ff00*/ + /* - * Bits in PPro special registers + * The R2000/R3000-specific status register bit definitions. + * all bits are active when set to 1. + * + * MIPS_SR_PARITY_ERR Parity error. + * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. + * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. + * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. + * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. + * Interrupt enable bits defined below. + * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. + * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. + * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. + * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. + * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. */ -#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ -#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ -#define CR4_TSD 0x00000004 /* Time stamp disable */ -#define CR4_DE 0x00000008 /* Debugging extensions */ -#define CR4_PSE 0x00000010 /* Page size extensions */ -#define CR4_PAE 0x00000020 /* Physical address extension */ -#define CR4_MCE 0x00000040 /* Machine check enable */ -#define CR4_PGE 0x00000080 /* Page global enable */ -#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ -#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ -#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ + +#define MIPS1_PARITY_ERR 0x00100000 +#define MIPS1_CACHE_MISS 0x00080000 +#define MIPS1_PARITY_ZERO 0x00040000 +#define MIPS1_SWAP_CACHES 0x00020000 +#define MIPS1_ISOL_CACHES 0x00010000 + +#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ +#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ +#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ +#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ +#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ + +/* backwards compatibility */ +#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR +#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS +#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO +#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES +#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES + +#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD +#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD +#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV +#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR +#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV /* - * Bits in AMD64 special registers. EFER is 64 bits wide. + * R4000 status register bit definitons, + * where different from r2000/r3000. */ -#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ -#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ -#define EFER_LMA 0x000000400 /* Long mode active (R) */ -#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ +#define MIPS3_SR_XX 0x80000000 +#define MIPS3_SR_RP 0x08000000 +#define MIPS3_SR_FR 0x04000000 +#define MIPS3_SR_RE 0x02000000 + +#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ +#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ +#define MIPS3_SR_SR 0x00100000 +#define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */ +#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ +#define MIPS3_SR_DIAG_CH 0x00040000 +#define MIPS3_SR_DIAG_CE 0x00020000 +#define MIPS3_SR_DIAG_PE 0x00010000 +#define MIPS3_SR_KX 0x00000080 +#define MIPS3_SR_SX 0x00000040 +#define MIPS3_SR_UX 0x00000020 +#define MIPS3_SR_KSU_MASK 0x00000018 +#define MIPS3_SR_KSU_USER 0x00000010 +#define MIPS3_SR_KSU_SUPER 0x00000008 +#define MIPS3_SR_KSU_KERNEL 0x00000000 +#define MIPS3_SR_ERL 0x00000004 +#define MIPS3_SR_EXL 0x00000002 + +#ifdef MIPS3_5900 +#undef MIPS_SR_INT_IE +#define MIPS_SR_INT_IE 0x00010001 /* XXX */ +#endif + +#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET +#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH +#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE +#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE +#define MIPS_SR_KX MIPS3_SR_KX +#define MIPS_SR_SX MIPS3_SR_SX +#define MIPS_SR_UX MIPS3_SR_UX + +#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK +#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER +#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER +#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL +#define MIPS_SR_ERL MIPS3_SR_ERL +#define MIPS_SR_EXL MIPS3_SR_EXL + /* - * CPUID instruction features register + * The interrupt masks. + * If a bit in the mask is 1 then the interrupt is enabled (or pending). */ -#define CPUID_FPU 0x00000001 -#define CPUID_VME 0x00000002 -#define CPUID_DE 0x00000004 -#define CPUID_PSE 0x00000008 -#define CPUID_TSC 0x00000010 -#define CPUID_MSR 0x00000020 -#define CPUID_PAE 0x00000040 -#define CPUID_MCE 0x00000080 -#define CPUID_CX8 0x00000100 -#define CPUID_APIC 0x00000200 -#define CPUID_B10 0x00000400 -#define CPUID_SEP 0x00000800 -#define CPUID_MTRR 0x00001000 -#define CPUID_PGE 0x00002000 -#define CPUID_MCA 0x00004000 -#define CPUID_CMOV 0x00008000 -#define CPUID_PAT 0x00010000 -#define CPUID_PSE36 0x00020000 -#define CPUID_PSN 0x00040000 -#define CPUID_CLFSH 0x00080000 -#define CPUID_B20 0x00100000 -#define CPUID_DS 0x00200000 -#define CPUID_ACPI 0x00400000 -#define CPUID_MMX 0x00800000 -#define CPUID_FXSR 0x01000000 -#define CPUID_SSE 0x02000000 -#define CPUID_XMM 0x02000000 -#define CPUID_SSE2 0x04000000 -#define CPUID_SS 0x08000000 -#define CPUID_HTT 0x10000000 -#define CPUID_TM 0x20000000 -#define CPUID_B30 0x40000000 -#define CPUID_PBE 0x80000000 +#define MIPS_INT_MASK 0xff00 +#define MIPS_INT_MASK_5 0x8000 +#define MIPS_INT_MASK_4 0x4000 +#define MIPS_INT_MASK_3 0x2000 +#define MIPS_INT_MASK_2 0x1000 +#define MIPS_INT_MASK_1 0x0800 +#define MIPS_INT_MASK_0 0x0400 +#define MIPS_HARD_INT_MASK 0xfc00 +#define MIPS_SOFT_INT_MASK_1 0x0200 +#define MIPS_SOFT_INT_MASK_0 0x0100 -#define CPUID2_SSE3 0x00000001 -#define CPUID2_MON 0x00000008 -#define CPUID2_DS_CPL 0x00000010 -#define CPUID2_EST 0x00000080 -#define CPUID2_TM2 0x00000100 -#define CPUID2_CNTXID 0x00000400 -#define CPUID2_CX16 0x00002000 +/* + * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can + * choose to enable this interrupt. + */ +#if defined(MIPS3_ENABLE_CLOCK_INTR) +#define MIPS3_INT_MASK MIPS_INT_MASK +#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK +#else +#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) +#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) +#endif /* - * Important bits in the AMD extended cpuid flags + * The bits in the context register. */ -#define AMDID_SYSCALL 0x00000800 -#define AMDID_MP 0x00080000 -#define AMDID_NX 0x00100000 -#define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 -#define AMDID_RDTSCP 0x08000000 -#define AMDID_LM 0x20000000 -#define AMDID_EXT_3DNOW 0x40000000 -#define AMDID_3DNOW 0x80000000 +#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 +#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC -#define AMDID2_LAHF 0x00000001 -#define AMDID2_CMP 0x00000002 -#define AMDID2_CR8 0x00000010 +#define MIPS3_CNTXT_PTE_BASE 0xFF800000 +#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 /* - * CPUID instruction 1 ebx info + * The bits in the MIPS3 config register. + * + * bit 0..5: R/W, Bit 6..31: R/O */ -#define CPUID_BRAND_INDEX 0x000000ff -#define CPUID_CLFUSH_SIZE 0x0000ff00 -#define CPUID_HTT_CORES 0x00ff0000 -#define CPUID_LOCAL_APIC_ID 0xff000000 + +/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ +#define MIPS3_CONFIG_K0_MASK 0x00000007 /* - * AMD extended function 8000_0008h ecx info + * R/W Update on Store Conditional + * 0: Store Conditional uses coherency algorithm specified by TLB + * 1: Store Conditional uses cacheable coherent update on write */ -#define AMDID_CMP_CORES 0x000000ff +#define MIPS3_CONFIG_CU 0x00000008 + +#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ +#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ +#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ + (((config) & (bit)) ? 32 : 16) + +#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ +#define MIPS3_CONFIG_DC_SHIFT 6 +#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ +#define MIPS3_CONFIG_IC_SHIFT 9 +#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ + +/* Cache size mode indication: available only on Vr41xx CPUs */ +#define MIPS3_CONFIG_CS 0x00001000 +#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ +#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ + ((base) << (((config) & (mask)) >> (shift))) + +/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ +#define MIPS3_CONFIG_SE 0x00001000 + +/* Block ordering: 0: sequential, 1: sub-block */ +#define MIPS3_CONFIG_EB 0x00002000 + +/* ECC mode - 0: ECC mode, 1: parity mode */ +#define MIPS3_CONFIG_EM 0x00004000 + +/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ +#define MIPS3_CONFIG_BE 0x00008000 + +/* Dirty Shared coherency state - 0: enabled, 1: disabled */ +#define MIPS3_CONFIG_SM 0x00010000 + +/* Secondary Cache - 0: present, 1: not present */ +#define MIPS3_CONFIG_SC 0x00020000 + +/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ +#define MIPS3_CONFIG_EW_MASK 0x000c0000 +#define MIPS3_CONFIG_EW_SHIFT 18 + +/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ +#define MIPS3_CONFIG_SW 0x00100000 + +/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ +#define MIPS3_CONFIG_SS 0x00200000 + +/* Secondary Cache line size */ +#define MIPS3_CONFIG_SB_MASK 0x00c00000 +#define MIPS3_CONFIG_SB_SHIFT 22 +#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ + (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) + +/* Write back data rate */ +#define MIPS3_CONFIG_EP_MASK 0x0f000000 +#define MIPS3_CONFIG_EP_SHIFT 24 + +/* System clock ratio - this value is CPU dependent */ +#define MIPS3_CONFIG_EC_MASK 0x70000000 +#define MIPS3_CONFIG_EC_SHIFT 28 + +/* Master-Checker Mode - 1: enabled */ +#define MIPS3_CONFIG_CM 0x80000000 /* - * Model-specific registers for the i386 family + * The bits in the MIPS4 config register. */ -#define MSR_P5_MC_ADDR 0x000 -#define MSR_P5_MC_TYPE 0x001 -#define MSR_TSC 0x010 -#define MSR_P5_CESR 0x011 -#define MSR_P5_CTR0 0x012 -#define MSR_P5_CTR1 0x013 -#define MSR_IA32_PLATFORM_ID 0x017 -#define MSR_APICBASE 0x01b -#define MSR_EBL_CR_POWERON 0x02a -#define MSR_TEST_CTL 0x033 -#define MSR_BIOS_UPDT_TRIG 0x079 -#define MSR_BBL_CR_D0 0x088 -#define MSR_BBL_CR_D1 0x089 -#define MSR_BBL_CR_D2 0x08a -#define MSR_BIOS_SIGN 0x08b -#define MSR_PERFCTR0 0x0c1 -#define MSR_PERFCTR1 0x0c2 -#define MSR_MTRRcap 0x0fe -#define MSR_BBL_CR_ADDR 0x116 -#define MSR_BBL_CR_DECC 0x118 -#define MSR_BBL_CR_CTL 0x119 -#define MSR_BBL_CR_TRIG 0x11a -#define MSR_BBL_CR_BUSY 0x11b -#define MSR_BBL_CR_CTL3 0x11e -#define MSR_SYSENTER_CS_MSR 0x174 -#define MSR_SYSENTER_ESP_MSR 0x175 -#define MSR_SYSENTER_EIP_MSR 0x176 -#define MSR_MCG_CAP 0x179 -#define MSR_MCG_STATUS 0x17a -#define MSR_MCG_CTL 0x17b -#define MSR_EVNTSEL0 0x186 -#define MSR_EVNTSEL1 0x187 -#define MSR_THERM_CONTROL 0x19a -#define MSR_THERM_INTERRUPT 0x19b -#define MSR_THERM_STATUS 0x19c -#define MSR_DEBUGCTLMSR 0x1d9 -#define MSR_LASTBRANCHFROMIP 0x1db -#define MSR_LASTBRANCHTOIP 0x1dc -#define MSR_LASTINTFROMIP 0x1dd -#define MSR_LASTINTTOIP 0x1de -#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 -#define MSR_MTRRVarBase 0x200 -#define MSR_MTRR64kBase 0x250 -#define MSR_MTRR16kBase 0x258 -#define MSR_MTRR4kBase 0x268 -#define MSR_PAT 0x277 -#define MSR_MTRRdefType 0x2ff -#define MSR_MC0_CTL 0x400 -#define MSR_MC0_STATUS 0x401 -#define MSR_MC0_ADDR 0x402 -#define MSR_MC0_MISC 0x403 -#define MSR_MC1_CTL 0x404 -#define MSR_MC1_STATUS 0x405 -#define MSR_MC1_ADDR 0x406 -#define MSR_MC1_MISC 0x407 -#define MSR_MC2_CTL 0x408 -#define MSR_MC2_STATUS 0x409 -#define MSR_MC2_ADDR 0x40a -#define MSR_MC2_MISC 0x40b -#define MSR_MC3_CTL 0x40c -#define MSR_MC3_STATUS 0x40d -#define MSR_MC3_ADDR 0x40e -#define MSR_MC3_MISC 0x40f -#define MSR_MC4_CTL 0x410 -#define MSR_MC4_STATUS 0x411 -#define MSR_MC4_ADDR 0x412 -#define MSR_MC4_MISC 0x413 + +/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ +#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK +#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ +#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ +#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ +#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ +#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ +#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ +#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ +#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ +#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ +#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ +#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ +#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ +#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ + +#define MIPS4_CONFIG_DC_SHIFT 26 +#define MIPS4_CONFIG_IC_SHIFT 29 + +#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ + ((base) << (((config) & (mask)) >> (shift))) + +#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ + (((config) & MIPS4_CONFIG_SB) ? 128 : 64) /* - * Constants related to MSR's. + * Location of exception vectors. + * + * Common vectors: reset and UTLB miss. */ -#define APICBASE_RESERVED 0x000006ff -#define APICBASE_BSP 0x00000100 -#define APICBASE_ENABLED 0x00000800 -#define APICBASE_ADDRESS 0xfffff000 +#define MIPS_RESET_EXC_VEC 0xBFC00000 +#define MIPS_UTLB_MISS_EXC_VEC 0x80000000 /* - * PAT modes. + * MIPS-1 general exception vector (everything else) */ -#define PAT_UNCACHEABLE 0x00 -#define PAT_WRITE_COMBINING 0x01 -#define PAT_WRITE_THROUGH 0x04 -#define PAT_WRITE_PROTECTED 0x05 -#define PAT_WRITE_BACK 0x06 -#define PAT_UNCACHED 0x07 -#define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) -#define PAT_MASK(i) PAT_VALUE(i, 0xff) +#define MIPS1_GEN_EXC_VEC 0x80000080 /* - * Constants related to MTRRs + * MIPS-III exception vectors */ -#define MTRR_N64K 8 /* numbers of fixed-size entries */ -#define MTRR_N16K 16 -#define MTRR_N4K 64 +#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 +#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 +#define MIPS3_GEN_EXC_VEC 0x80000180 -/* Performance Control Register (5x86 only). */ -#define PCR0 0x20 -#define PCR0_RSTK 0x01 /* Enables return stack */ -#define PCR0_BTB 0x02 /* Enables branch target buffer */ -#define PCR0_LOOP 0x04 /* Enables loop */ -#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to - serialize pipe. */ -#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ -#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ -#define PCR0_LSSER 0x80 /* Disable reorder */ +/* + * TX79 (R5900) exception vectors + */ +#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 +#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 -/* Device Identification Registers */ -#define DIR0 0xfe -#define DIR1 0xff +/* + * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. + */ +#define MIPS3_INTR_EXC_VEC 0x80000200 /* - * The following four 3-byte registers control the non-cacheable regions. - * These registers must be written as three separate bytes. + * Coprocessor 0 registers: * - * NCRx+0: A31-A24 of starting address - * NCRx+1: A23-A16 of starting address - * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. - * - * The non-cacheable region's starting address must be aligned to the - * size indicated by the NCR_SIZE_xx field. + * v--- width for mips I,III,32,64 + * (3=32bit, 6=64bit, i=impl dep) + * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. + * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. + * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. + * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. + * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. + * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. + * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. + * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. + * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. + * 9 MIPS_COP_0_COUNT .333 Count register. + * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. + * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). + * 12 MIPS_COP_0_STATUS 3333 Status register. + * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. + * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. + * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. + * 16 MIPS_COP_0_CONFIG 3333 Configuration register. + * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. + * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. + * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. + * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. + * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. + * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. + * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. + * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. + * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. + * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. + * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. + * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. + * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). + * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). + * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). + * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). + * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). + * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). + * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). + * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). + * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. + * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. + */ +#ifdef _LOCORE +#define _(n) __CONCAT($,n) +#else +#define _(n) n +#endif +#define MIPS_COP_0_TLB_INDEX _(0) +#define MIPS_COP_0_TLB_RANDOM _(1) + /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ + +#define MIPS_COP_0_TLB_CONTEXT _(4) + /* $5 and $6 new with MIPS-III */ +#define MIPS_COP_0_BAD_VADDR _(8) +#define MIPS_COP_0_TLB_HI _(10) +#define MIPS_COP_0_STATUS _(12) +#define MIPS_COP_0_CAUSE _(13) +#define MIPS_COP_0_EXC_PC _(14) +#define MIPS_COP_0_PRID _(15) + + +/* MIPS-I */ +#define MIPS_COP_0_TLB_LOW _(2) + +/* MIPS-III */ +#define MIPS_COP_0_TLB_LO0 _(2) +#define MIPS_COP_0_TLB_LO1 _(3) + +#define MIPS_COP_0_TLB_PG_MASK _(5) +#define MIPS_COP_0_TLB_WIRED _(6) + +#define MIPS_COP_0_COUNT _(9) +#define MIPS_COP_0_COMPARE _(11) + +#define MIPS_COP_0_CONFIG _(16) +#define MIPS_COP_0_LLADDR _(17) +#define MIPS_COP_0_WATCH_LO _(18) +#define MIPS_COP_0_WATCH_HI _(19) +#define MIPS_COP_0_TLB_XCONTEXT _(20) +#define MIPS_COP_0_ECC _(26) +#define MIPS_COP_0_CACHE_ERR _(27) +#define MIPS_COP_0_TAG_LO _(28) +#define MIPS_COP_0_TAG_HI _(29) +#define MIPS_COP_0_ERROR_PC _(30) + +/* MIPS32/64 */ +#define MIPS_COP_0_DEBUG _(23) +#define MIPS_COP_0_DEPC _(24) +#define MIPS_COP_0_PERFCNT _(25) +#define MIPS_COP_0_DATA_LO _(28) +#define MIPS_COP_0_DATA_HI _(29) +#define MIPS_COP_0_DESAVE _(31) + +/* + * Values for the code field in a break instruction. + */ +#define MIPS_BREAK_INSTR 0x0000000d +#define MIPS_BREAK_VAL_MASK 0x03ff0000 +#define MIPS_BREAK_VAL_SHIFT 16 +#define MIPS_BREAK_KDB_VAL 512 +#define MIPS_BREAK_SSTEP_VAL 513 +#define MIPS_BREAK_BRKPT_VAL 514 +#define MIPS_BREAK_SOVER_VAL 515 +#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ + (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) +#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ + (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) +#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ + (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) +#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ + (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) + +/* + * Mininum and maximum cache sizes. + */ +#define MIPS_MIN_CACHE_SIZE (16 * 1024) +#define MIPS_MAX_CACHE_SIZE (256 * 1024) +#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ + +/* + * The floating point version and status registers. + */ +#define MIPS_FPU_ID $0 +#define MIPS_FPU_CSR $31 + +/* + * The floating point coprocessor status register bits. + */ +#define MIPS_FPU_ROUNDING_BITS 0x00000003 +#define MIPS_FPU_ROUND_RN 0x00000000 +#define MIPS_FPU_ROUND_RZ 0x00000001 +#define MIPS_FPU_ROUND_RP 0x00000002 +#define MIPS_FPU_ROUND_RM 0x00000003 +#define MIPS_FPU_STICKY_BITS 0x0000007c +#define MIPS_FPU_STICKY_INEXACT 0x00000004 +#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 +#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 +#define MIPS_FPU_STICKY_DIV0 0x00000020 +#define MIPS_FPU_STICKY_INVALID 0x00000040 +#define MIPS_FPU_ENABLE_BITS 0x00000f80 +#define MIPS_FPU_ENABLE_INEXACT 0x00000080 +#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 +#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 +#define MIPS_FPU_ENABLE_DIV0 0x00000400 +#define MIPS_FPU_ENABLE_INVALID 0x00000800 +#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 +#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 +#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 +#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 +#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 +#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 +#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 +#define MIPS_FPU_COND_BIT 0x00800000 +#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ +#define MIPS1_FPC_MBZ_BITS 0xff7c0000 +#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 + + +/* + * Constants to determine if have a floating point instruction. + */ +#define MIPS_OPCODE_SHIFT 26 +#define MIPS_OPCODE_C1 0x11 + + +/* + * The low part of the TLB entry. + */ +#define MIPS1_TLB_PFN 0xfffff000 +#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 +#define MIPS1_TLB_DIRTY_BIT 0x00000400 +#define MIPS1_TLB_VALID_BIT 0x00000200 +#define MIPS1_TLB_GLOBAL_BIT 0x00000100 + +#define MIPS3_TLB_PFN 0x3fffffc0 +#define MIPS3_TLB_ATTR_MASK 0x00000038 +#define MIPS3_TLB_ATTR_SHIFT 3 +#define MIPS3_TLB_DIRTY_BIT 0x00000004 +#define MIPS3_TLB_VALID_BIT 0x00000002 +#define MIPS3_TLB_GLOBAL_BIT 0x00000001 + +#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 +#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 +#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN +#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN +#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT +#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT + +/* + * MIPS3_TLB_ATTR values - coherency algorithm: + * 0: cacheable, noncoherent, write-through, no write allocate + * 1: cacheable, noncoherent, write-through, write allocate + * 2: uncached + * 3: cacheable, noncoherent, write-back (noncoherent) + * 4: cacheable, coherent, write-back, exclusive (exclusive) + * 5: cacheable, coherent, write-back, exclusive on write (sharable) + * 6: cacheable, coherent, write-back, update on write (update) + * 7: uncached, accelerated (gather STORE operations) + */ +#define MIPS3_TLB_ATTR_WT 0 /* IDT */ +#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ +#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ +#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ +#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ +#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ +#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ +#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ + + +/* + * The high part of the TLB entry. + */ +#define MIPS1_TLB_VPN 0xfffff000 +#define MIPS1_TLB_PID 0x00000fc0 +#define MIPS1_TLB_PID_SHIFT 6 + +#define MIPS3_TLB_VPN2 0xffffe000 +#define MIPS3_TLB_ASID 0x000000ff + +#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN +#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 +#define MIPS3_TLB_PID MIPS3_TLB_ASID +#define MIPS_TLB_VIRT_PAGE_SHIFT 12 + +/* + * r3000: shift count to put the index in the right spot. + */ +#define MIPS1_TLB_INDEX_SHIFT 8 + +/* + * The first TLB that write random hits. + */ +#define MIPS1_TLB_FIRST_RAND_ENTRY 8 +#define MIPS3_TLB_WIRED_UPAGES 1 + +/* + * The number of process id entries. + */ +#define MIPS1_TLB_NUM_PIDS 64 +#define MIPS3_TLB_NUM_ASIDS 256 + +/* + * Patch codes to hide CPU design differences between MIPS1 and MIPS3. + */ + +/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ + +#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ + && defined(MIPS1) /* XXX simonb must be neater! */ +#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT +#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS +#endif + +#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ + && !defined(MIPS1) /* XXX simonb must be neater! */ +#define MIPS_TLB_PID_SHIFT 0 +#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS +#endif + + +#if !defined(MIPS_TLB_PID_SHIFT) +#define MIPS_TLB_PID_SHIFT \ + ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) + +#define MIPS_TLB_NUM_PIDS \ + ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) +#endif + +/* + * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) + */ +#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ +#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ +#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ +#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ +#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ +#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ +#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ +#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ +#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ +#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ +#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ +#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ +#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ +#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ +#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ +#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ +#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ +#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ +#define MIPS_R4650 0x22 /* QED R4650 ISA III */ +#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ +#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ +#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ +#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ +#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ +#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ +#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ +#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ +#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ +#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ +#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ +#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ + +/* + * CPU revision IDs for some prehistoric processors. */ -#define NCR1 0xc4 -#define NCR2 0xc7 -#define NCR3 0xca -#define NCR4 0xcd + +/* For MIPS_R3000 */ +#define MIPS_REV_R3000 0x20 +#define MIPS_REV_R3000A 0x30 + +/* For MIPS_TX3900 */ +#define MIPS_REV_TX3912 0x10 +#define MIPS_REV_TX3922 0x30 +#define MIPS_REV_TX3927 0x40 + +/* For MIPS_R4000 */ +#define MIPS_REV_R4000_A 0x00 +#define MIPS_REV_R4000_B 0x22 +#define MIPS_REV_R4000_C 0x30 +#define MIPS_REV_R4400_A 0x40 +#define MIPS_REV_R4400_B 0x50 +#define MIPS_REV_R4400_C 0x60 -#define NCR_SIZE_0K 0 -#define NCR_SIZE_4K 1 -#define NCR_SIZE_8K 2 -#define NCR_SIZE_16K 3 -#define NCR_SIZE_32K 4 -#define NCR_SIZE_64K 5 -#define NCR_SIZE_128K 6 -#define NCR_SIZE_256K 7 -#define NCR_SIZE_512K 8 -#define NCR_SIZE_1M 9 -#define NCR_SIZE_2M 10 -#define NCR_SIZE_4M 11 -#define NCR_SIZE_8M 12 -#define NCR_SIZE_16M 13 -#define NCR_SIZE_32M 14 -#define NCR_SIZE_4G 15 +/* For MIPS_TX4900 */ +#define MIPS_REV_TX4927 0x22 /* - * The address region registers are used to specify the location and - * size for the eight address regions. - * - * ARRx + 0: A31-A24 of start address - * ARRx + 1: A23-A16 of start address - * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx + * CPU processor revision IDs for company ID == 1 (MIPS) */ -#define ARR0 0xc4 -#define ARR1 0xc7 -#define ARR2 0xca -#define ARR3 0xcd -#define ARR4 0xd0 -#define ARR5 0xd3 -#define ARR6 0xd6 -#define ARR7 0xd9 +#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ +#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ +#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ +#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ +#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ +#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ >>> TRUNCATED FOR MAIL (1000 lines) <<<
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