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Date:      Tue, 29 Jun 1999 16:05:57 -0400
From:      Richard Cownie <tich@ma.ikos.com>
To:        Kevin Van Maren <vanmaren@fast.cs.utah.edu>, freebsd-smp@FreeBSD.ORG, tich@ma.ikos.com, vanmaren@cs.utah.edu
Subject:   Re: high-efficiency SMP locks - submission for review
Message-ID:  <99062916234600.22336@par28.ma.ikos.com>
References:  <199906291908.NAA08028@fast.cs.utah.edu>

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On Tue, 29 Jun 1999, Kevin Van Maren wrote:
> > No, you can have a non-aligned locked access - there's a bunch of
> > complex and ugly stuff ("split locks", the SPLCK# bus signal) in
> > the P6 bus protocol to support this. But don't do it if you can
> > possibly avoid it - it's inefficient, and since it exercises arcane
> > features of the hardware, it could be buggy.  
> 
> My understanding is that it is only guaranteed to be atomic for the
> processor family if it is naturally-aligned, although current
> processors ALSO provide atomic operatings for unaligned accesses.
> My point is that we should not rely on unaligned accesses being
> atomic, as per intel documentation.

I've never really been convinced that there's a rigorous definition of
the x86 family architecture, as distinct from what the particular
implementations happen to do.  Or where there *is* a specification,
Intel feels quite free to violate it (e.g. the MPS spec says that
you can mix different CPU's - but the truth for the P6/PentiumII/PentiumIII
is that all the CPU's in an SMP system need to be the exact same stepping).

On the other hand, there's so much weird software out there that Intel
will probably never allow themselves to remove any feature that might
possibly be used in some application somewhere.  So I'd bet that future
cpu's will continue to support atomic misaligned read-modify-write.

However, it doesn't seem that there's any good reason to use this 
particular feature.  It's easy to get stuff aligned, and much more efficient.

Richard Cownie


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