From owner-freebsd-mobile@FreeBSD.ORG Thu Oct 16 17:20:24 2003 Return-Path: Delivered-To: freebsd-mobile@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 10CA116A4B3; Thu, 16 Oct 2003 17:20:24 -0700 (PDT) Received: from mail.tel.fer.hr (zg05-018.dialin.iskon.hr [213.191.138.19]) by mx1.FreeBSD.org (Postfix) with ESMTP id E800F43FE1; Thu, 16 Oct 2003 17:20:20 -0700 (PDT) (envelope-from zec@tel.fer.hr) Received: from 192.168.200.114 (marko@dhcp14.katoda.net [192.168.200.114]) by mail.tel.fer.hr (8.12.6/8.12.6) with ESMTP id h9H0Kgi3001698; Fri, 17 Oct 2003 02:20:45 +0200 (CEST) (envelope-from zec@tel.fer.hr) From: Marko Zec To: freebsd-mobile@freebsd.org, freebsd-hackers@freebsd.org Date: Fri, 17 Oct 2003 02:20:25 +0200 User-Agent: KMail/1.5 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200310170220.25356.zec@tel.fer.hr> Subject: PATCH: Pentium-M deeper sleep support in idle loop X-BeenThere: freebsd-mobile@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Mobile computing with FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Oct 2003 00:20:24 -0000 >From http://www.tel.fer.hr/zec/BSD/pm/4.8-ich-ds.patch you can fetch an experimental patch for the 4.8-RELEASE kernel that allows for significant power savings on mobile systems by utilizing a feature called "deeper sleep mode". The deeper sleep mode is available on recent Intel mobile processors (Pentium III-M, Pentium IV-M and "Centrino" Mobile Pentium) in combination with ICH3 / ICH4 chipsets, and is used to simultaneously stop the CPU clock and significantly lower the chip core voltage. When in such a state, the CPU is supposed to consume only around 0.6 W, according to Intel specs. The power saving policy in idle loop is controlled by the machdep.cpu_idle_hlt sysctl, which now has two new modes: Mode 0 (std) Do not halt the CPU, return from the idle loop as soon as possible. Mode 1 (std) Halt the CPU using the "hlt" instruction. CPU clock is not stopped (TSC keeps counting). Mode 2 (new) Halt the CPU using APM BIOS call followed by a "hlt". This method stops the clock, thus saving slightly more power. Mode 3 (new) Halt the CPU by entering the deeper sleep mode (max. power savings). The battery life extension that can be obtained on an idle system using this patch looks very promissing. Here's what I could observe on my ThinkPad X30 (Pentium III-M 1200, ICH-3 chipset) with a slightly worn-out battery: +---------+----------------------+----------------------+ |cpu_idle | LCD ON (dim) | LCD OFF | | mode | Bat. life | gain | Bat. life | gain | +---------+-----------+----------+-----------+----------+ | 1 | 4:03 | | 5:12 | | +---------+-----------+----------+-----------+----------+ | 2 | 4:10 | 2% | 5:23 | 3% | +---------+-----------+----------+-----------+----------+ | 3 | 4:48 | 18% | 6:21 | 22% | +---------+-----------+----------+-----------+----------+ I had no ICH-4 based laptop available for testing, so I cannot promise that the patch will work on such systems, although it should. The patch also introduces a new sysctl machdep.speedstep, which can be used to directly controll the CPU clock frequency / operating voltage. If your BIOS already correctly does this job you probably won't need this sysctl, however the BIOS in my ThinkPad annoyingly persists with the same speedstep mode regardless of the power source (external/battery), so I had to implement a method to control it. Anyhow, hope you like the patch... The usual liability disclaimer applies - if anything goes wrong with your machinery or data, you are on your own :-) Have fun, Marko