Date: Sat, 22 Aug 2015 07:32:48 +0000 (UTC) From: Alexander Motin <mav@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r287016 - in stable/10: . share/man/man4 sys/arm/mv sys/boot/forth sys/conf sys/dev/ata sys/dev/ata/chipsets sys/modules/ata/atapci/chipsets sys/modules/ata/atapci/chipsets/ataadaptec s... Message-ID: <201508220732.t7M7WmJ0053866@repo.freebsd.org>
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Author: mav Date: Sat Aug 22 07:32:47 2015 New Revision: 287016 URL: https://svnweb.freebsd.org/changeset/base/287016 Log: MFC r280451: Remove from legacy ata(4) driver support for hardware, supported by newer and more functional drivers ahci(4), siis(4) and mvs(4). This removes about 3400 lines of code, unused since FreeBSD 9.0 release. Deleted: stable/10/sys/arm/mv/mv_sata.c stable/10/sys/dev/ata/chipsets/ata-adaptec.c stable/10/sys/dev/ata/chipsets/ata-ahci.c stable/10/sys/modules/ata/atapci/chipsets/ataadaptec/ stable/10/sys/modules/ata/atapci/chipsets/ataahci/ Modified: stable/10/UPDATING stable/10/share/man/man4/ahci.4 stable/10/share/man/man4/ata.4 stable/10/share/man/man4/mvs.4 stable/10/share/man/man4/siis.4 stable/10/sys/arm/mv/files.mv stable/10/sys/boot/forth/loader.conf stable/10/sys/conf/NOTES stable/10/sys/conf/files stable/10/sys/dev/ata/ata-all.h stable/10/sys/dev/ata/ata-pci.h stable/10/sys/dev/ata/chipsets/ata-acerlabs.c stable/10/sys/dev/ata/chipsets/ata-ati.c stable/10/sys/dev/ata/chipsets/ata-intel.c stable/10/sys/dev/ata/chipsets/ata-jmicron.c stable/10/sys/dev/ata/chipsets/ata-marvell.c stable/10/sys/dev/ata/chipsets/ata-nvidia.c stable/10/sys/dev/ata/chipsets/ata-siliconimage.c stable/10/sys/dev/ata/chipsets/ata-via.c stable/10/sys/modules/ata/atapci/chipsets/Makefile Directory Properties: stable/10/ (props changed) Modified: stable/10/UPDATING ============================================================================== --- stable/10/UPDATING Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/UPDATING Sat Aug 22 07:32:47 2015 (r287016) @@ -16,6 +16,12 @@ from older versions of FreeBSD, try WITH stable/10, and then rebuild without this option. The bootstrap process from older version of current is a bit fragile. +20150822: + From legacy ata(4) driver was removed support for SATA controllers + supported by more functional drivers ahci(4), siis(4) and mvs(4). + Kernel modules ataahci and ataadaptec were removed completely, + replaced by ahci and mvs modules respectively. + 20150813: 10.2-RELEASE. Modified: stable/10/share/man/man4/ahci.4 ============================================================================== --- stable/10/share/man/man4/ahci.4 Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/share/man/man4/ahci.4 Sat Aug 22 07:32:47 2015 (r287016) @@ -138,12 +138,6 @@ device for localization and status repor Supporting AHCI controllers may transmit that information to the backplane controllers via SGPIO interface. Backplane controllers interpret received statuses in some way (IBPI standard) to report them using present indicators. -.Pp -AHCI hardware is also supported by ataahci driver from -.Xr ata 4 -subsystem. -If both drivers are loaded at the same time, this one will be -given precedence as the more functional of the two. .Sh HARDWARE The .Nm Modified: stable/10/share/man/man4/ata.4 ============================================================================== --- stable/10/share/man/man4/ata.4 Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/share/man/man4/ata.4 Sat Aug 22 07:32:47 2015 (r287016) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd October 3, 2012 +.Dd March 23, 2015 .Dt ATA 4 .Os .Sh NAME @@ -50,8 +50,6 @@ atapci_load="YES" ataacard_load="YES" ataacerlabs_load="YES" -ataadaptec_load="YES" -ataahci_load="YES" ataamd_load="YES" ataati_load="YES" atacenatek_load="YES" @@ -76,16 +74,11 @@ atavia_load="YES" The first line is for the common hardware independent code, and is a prerequisite for the other modules. The next three lines are generic bus-specific drivers. -Of the rest, ataahci is the AHCI driver. -The others are vendor-specific PCI drivers. +The rest are vendor-specific PCI drivers. .Pp The following tunables are settable from the .Xr loader 8 : .Bl -ohang -.It Va hw.ahci.force -set to nonzero value for forcing drivers to attach to some known AHCI-capable -chips even if they are configured for legacy IDE emulation (the default is 1, -force the attach). .It Va hw.ata.ata_dma_check_80pin set to 0 to disable the 80pin cable check (the default is 1, check the cable). .It Va hint.atapci.X.msi @@ -106,13 +99,6 @@ Interface Power Management is disabled. This is the default value. .It 1 The device is allowed to initiate a PM state change; the host is passive. -.It 2 -The host initiates a PARTIAL PM state transition every time a port becomes idle. -.It 3 -host initiates SLUMBER PM state transition every time port becomes idle. -.El -.Pp -Modes 2 and 3 are only supported for AHCI. .It Va hint.ata. Ns Ar X Ns Va .dev Ns Ar X Ns Va .sata_rev limits the initial SATA revision (speed) for the specified device on the specified channel. @@ -198,8 +184,7 @@ IT8211F, IT8212F, IT8213F. .It JMicron: JMB360, JMB361, JMB363, JMB365, JMB366, JMB368. .It Marvell -88SX5040, 88SX5041, 88SX5080, 88SX5081, 88SX6041, 88SX6042, 88SX6081, 88SE6101, -88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145, 88SX7042. +88SE6101, 88SE6102, 88SE6111, 88SE6121, 88SE6141, 88SE6145. .It National: SC1100. .It NetCell: @@ -216,7 +201,7 @@ PDC40718, PDC40719. .It ServerWorks: HT1000, ROSB4, CSB5, CSB6, K2, Frodo4, Frodo8. .It Silicon Image: -SiI0680, SiI3112, SiI3114, SiI3124, SiI3132, SiI3512. +SiI0680, SiI3112, SiI3114, SiI3512. .It SiS: SIS180, SIS181, SIS182, SIS5513, SIS530, SIS540, SIS550, SIS620, SIS630, SIS630S, SIS633, SIS635, SIS730, SIS733, SIS735, SIS745, SIS961, SIS962, @@ -227,13 +212,10 @@ VT82C686A, VT82C686B, VT8231, VT8233, VT VT8237A, VT8237S, VT8251, CX700, VX800, VX855, VX900. .El .Pp -Some of above chips are also supported by the more featured -.Xr ahci 4 , -.Xr mvs 4 , -and -.Xr siis 4 -drivers. -If both drivers are loaded at the same time, those will have precedence. +Some of above chips can be configured for AHCI mode. +In such case they are supported by +.Xr ahci 4 +driver instead. .Pp Unknown ATA chipsets are supported in PIO modes, and if the standard busmaster DMA registers are present and contain valid setup, DMA is Modified: stable/10/share/man/man4/mvs.4 ============================================================================== --- stable/10/share/man/man4/mvs.4 Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/share/man/man4/mvs.4 Sat Aug 22 07:32:47 2015 (r287016) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd March 3, 2013 +.Dd March 23, 2015 .Dt MVS 4 .Os .Sh NAME @@ -109,13 +109,6 @@ Port Multipliers (including FIS-based sw hardware command queues (up to 31 command per port), Native Command Queuing, SATA interface Power Management, device hot-plug and Message Signaled Interrupts. -.Pp -The same hardware is also supported by the atamarvell and ataadaptec -drivers from the -.Xr ata 4 -subsystem. -If both drivers are loaded at the same time, this one will be -given precedence as the more functional of the two. .Sh HARDWARE The .Nm Modified: stable/10/share/man/man4/siis.4 ============================================================================== --- stable/10/share/man/man4/siis.4 Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/share/man/man4/siis.4 Sat Aug 22 07:32:47 2015 (r287016) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 8, 2011 +.Dd March 23, 2015 .Dt SIIS 4 .Os .Sh NAME @@ -98,12 +98,6 @@ The activity LEDs of the adapters suppor driver can be controlled via the .Xr led 4 API for localization or status reporting purposes. -.Pp -Same hardware is also supported by the atasiliconimage driver from -.Xr ata 4 -subsystem. -If both drivers are loaded at the same time, this one will be -given precedence as the more functional of the two. .Sh HARDWARE The .Nm Modified: stable/10/sys/arm/mv/files.mv ============================================================================== --- stable/10/sys/arm/mv/files.mv Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/arm/mv/files.mv Sat Aug 22 07:32:47 2015 (r287016) @@ -27,7 +27,6 @@ arm/mv/mv_common.c standard arm/mv/mv_localbus.c standard arm/mv/mv_machdep.c standard arm/mv/mv_pci.c optional pci -arm/mv/mv_sata.c optional ata | atamvsata arm/mv/mv_ts.c standard arm/mv/timer.c standard arm/mv/twsi.c optional iicbus Modified: stable/10/sys/boot/forth/loader.conf ============================================================================== --- stable/10/sys/boot/forth/loader.conf Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/boot/forth/loader.conf Sat Aug 22 07:32:47 2015 (r287016) @@ -149,10 +149,8 @@ module_path="/boot/modules" # Set the mo ### ATA modules ############################################## ############################################################## -ataahci_load="NO" # AHCI SATA ataacard_load="NO" # ACARD ataacerlabs_load="NO" # Acer Labs Inc. (ALI) -ataadaptec_load="NO" # Adaptec ataamd_load="NO" # American Micro Devices (AMD) ataati_load="NO" # ATI atacenatek_load="NO" # Cenatek Modified: stable/10/sys/conf/NOTES ============================================================================== --- stable/10/sys/conf/NOTES Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/conf/NOTES Sat Aug 22 07:32:47 2015 (r287016) @@ -1719,10 +1719,8 @@ device ata #device atapci # PCI bus support; only generic chipset support # PCI ATA chipsets -#device ataahci # AHCI SATA #device ataacard # ACARD #device ataacerlabs # Acer Labs Inc. (ALI) -#device ataadaptec # Adaptec #device ataamd # American Micro Devices (AMD) #device ataati # ATI #device atacenatek # Cenatek Modified: stable/10/sys/conf/files ============================================================================== --- stable/10/sys/conf/files Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/conf/files Sat Aug 22 07:32:47 2015 (r287016) @@ -680,12 +680,8 @@ dev/ata/ata-card.c optional ata pccard dev/ata/ata-cbus.c optional ata pc98 | atapc98 dev/ata/ata-isa.c optional ata isa | ataisa dev/ata/ata-pci.c optional ata pci | atapci -dev/ata/chipsets/ata-ahci.c optional ata pci | ataahci | ataacerlabs | \ - ataati | ataintel | atajmicron | \ - atavia | atanvidia dev/ata/chipsets/ata-acard.c optional ata pci | ataacard dev/ata/chipsets/ata-acerlabs.c optional ata pci | ataacerlabs -dev/ata/chipsets/ata-adaptec.c optional ata pci | ataadaptec dev/ata/chipsets/ata-amd.c optional ata pci | ataamd dev/ata/chipsets/ata-ati.c optional ata pci | ataati dev/ata/chipsets/ata-cenatek.c optional ata pci | atacenatek @@ -695,7 +691,7 @@ dev/ata/chipsets/ata-highpoint.c optiona dev/ata/chipsets/ata-intel.c optional ata pci | ataintel dev/ata/chipsets/ata-ite.c optional ata pci | ataite dev/ata/chipsets/ata-jmicron.c optional ata pci | atajmicron -dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell | ataadaptec +dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell dev/ata/chipsets/ata-micron.c optional ata pci | atamicron dev/ata/chipsets/ata-national.c optional ata pci | atanational dev/ata/chipsets/ata-netcell.c optional ata pci | atanetcell Modified: stable/10/sys/dev/ata/ata-all.h ============================================================================== --- stable/10/sys/dev/ata/ata-all.h Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/ata-all.h Sat Aug 22 07:32:47 2015 (r287016) @@ -150,139 +150,6 @@ #define ATA_SACTIVE 16 -/* SATA AHCI v1.0 register defines */ -#define ATA_AHCI_CAP 0x00 -#define ATA_AHCI_CAP_NPMASK 0x0000001f -#define ATA_AHCI_CAP_SXS 0x00000020 -#define ATA_AHCI_CAP_EMS 0x00000040 -#define ATA_AHCI_CAP_CCCS 0x00000080 -#define ATA_AHCI_CAP_NCS 0x00001F00 -#define ATA_AHCI_CAP_NCS_SHIFT 8 -#define ATA_AHCI_CAP_PSC 0x00002000 -#define ATA_AHCI_CAP_SSC 0x00004000 -#define ATA_AHCI_CAP_PMD 0x00008000 -#define ATA_AHCI_CAP_FBSS 0x00010000 -#define ATA_AHCI_CAP_SPM 0x00020000 -#define ATA_AHCI_CAP_SAM 0x00080000 -#define ATA_AHCI_CAP_ISS 0x00F00000 -#define ATA_AHCI_CAP_ISS_SHIFT 20 -#define ATA_AHCI_CAP_SCLO 0x01000000 -#define ATA_AHCI_CAP_SAL 0x02000000 -#define ATA_AHCI_CAP_SALP 0x04000000 -#define ATA_AHCI_CAP_SSS 0x08000000 -#define ATA_AHCI_CAP_SMPS 0x10000000 -#define ATA_AHCI_CAP_SSNTF 0x20000000 -#define ATA_AHCI_CAP_SNCQ 0x40000000 -#define ATA_AHCI_CAP_64BIT 0x80000000 - -#define ATA_AHCI_GHC 0x04 -#define ATA_AHCI_GHC_AE 0x80000000 -#define ATA_AHCI_GHC_IE 0x00000002 -#define ATA_AHCI_GHC_HR 0x00000001 - -#define ATA_AHCI_IS 0x08 -#define ATA_AHCI_PI 0x0c -#define ATA_AHCI_VS 0x10 - -#define ATA_AHCI_OFFSET 0x80 - -#define ATA_AHCI_P_CLB 0x100 -#define ATA_AHCI_P_CLBU 0x104 -#define ATA_AHCI_P_FB 0x108 -#define ATA_AHCI_P_FBU 0x10c -#define ATA_AHCI_P_IS 0x110 -#define ATA_AHCI_P_IE 0x114 -#define ATA_AHCI_P_IX_DHR 0x00000001 -#define ATA_AHCI_P_IX_PS 0x00000002 -#define ATA_AHCI_P_IX_DS 0x00000004 -#define ATA_AHCI_P_IX_SDB 0x00000008 -#define ATA_AHCI_P_IX_UF 0x00000010 -#define ATA_AHCI_P_IX_DP 0x00000020 -#define ATA_AHCI_P_IX_PC 0x00000040 -#define ATA_AHCI_P_IX_DI 0x00000080 - -#define ATA_AHCI_P_IX_PRC 0x00400000 -#define ATA_AHCI_P_IX_IPM 0x00800000 -#define ATA_AHCI_P_IX_OF 0x01000000 -#define ATA_AHCI_P_IX_INF 0x04000000 -#define ATA_AHCI_P_IX_IF 0x08000000 -#define ATA_AHCI_P_IX_HBD 0x10000000 -#define ATA_AHCI_P_IX_HBF 0x20000000 -#define ATA_AHCI_P_IX_TFE 0x40000000 -#define ATA_AHCI_P_IX_CPD 0x80000000 - -#define ATA_AHCI_P_CMD 0x118 -#define ATA_AHCI_P_CMD_ST 0x00000001 -#define ATA_AHCI_P_CMD_SUD 0x00000002 -#define ATA_AHCI_P_CMD_POD 0x00000004 -#define ATA_AHCI_P_CMD_CLO 0x00000008 -#define ATA_AHCI_P_CMD_FRE 0x00000010 -#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 -#define ATA_AHCI_P_CMD_ISS 0x00002000 -#define ATA_AHCI_P_CMD_FR 0x00004000 -#define ATA_AHCI_P_CMD_CR 0x00008000 -#define ATA_AHCI_P_CMD_CPS 0x00010000 -#define ATA_AHCI_P_CMD_PMA 0x00020000 -#define ATA_AHCI_P_CMD_HPCP 0x00040000 -#define ATA_AHCI_P_CMD_ISP 0x00080000 -#define ATA_AHCI_P_CMD_CPD 0x00100000 -#define ATA_AHCI_P_CMD_ATAPI 0x01000000 -#define ATA_AHCI_P_CMD_DLAE 0x02000000 -#define ATA_AHCI_P_CMD_ALPE 0x04000000 -#define ATA_AHCI_P_CMD_ASP 0x08000000 -#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 -#define ATA_AHCI_P_CMD_NOOP 0x00000000 -#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 -#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 -#define ATA_AHCI_P_CMD_SLUMBER 0x60000000 - -#define ATA_AHCI_P_TFD 0x120 -#define ATA_AHCI_P_SIG 0x124 -#define ATA_AHCI_P_SSTS 0x128 -#define ATA_AHCI_P_SCTL 0x12c -#define ATA_AHCI_P_SERR 0x130 -#define ATA_AHCI_P_SACT 0x134 -#define ATA_AHCI_P_CI 0x138 -#define ATA_AHCI_P_SNTF 0x13C -#define ATA_AHCI_P_FBS 0x140 - -#define ATA_AHCI_CL_SIZE 32 -#define ATA_AHCI_CL_OFFSET 0 -#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) -#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) -#define ATA_AHCI_CT_SIZE (2176 + 128) - -struct ata_ahci_dma_prd { - u_int64_t dba; - u_int32_t reserved; - u_int32_t dbc; /* 0 based */ -#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ -#define ATA_AHCI_PRD_IPC (1<<31) -} __packed; - -struct ata_ahci_cmd_tab { - u_int8_t cfis[64]; - u_int8_t acmd[32]; - u_int8_t reserved[32]; -#define ATA_AHCI_DMA_ENTRIES 129 - struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; -} __packed; - -struct ata_ahci_cmd_list { - u_int16_t cmd_flags; -#define ATA_AHCI_CMD_ATAPI 0x0020 -#define ATA_AHCI_CMD_WRITE 0x0040 -#define ATA_AHCI_CMD_PREFETCH 0x0080 -#define ATA_AHCI_CMD_RESET 0x0100 -#define ATA_AHCI_CMD_BIST 0x0200 -#define ATA_AHCI_CMD_CLR_BUSY 0x0400 - - u_int16_t prd_length; /* PRD entries */ - u_int32_t bytecount; - u_int64_t cmd_table_phys; /* 128byte aligned */ -} __packed; - - /* DMA register defines */ #define ATA_DMA_ENTRIES 256 #define ATA_DMA_EOT 0x80000000 Modified: stable/10/sys/dev/ata/ata-pci.h ============================================================================== --- stable/10/sys/dev/ata/ata-pci.h Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/ata-pci.h Sat Aug 22 07:32:47 2015 (r287016) @@ -169,93 +169,49 @@ struct ata_pci_controller { #define ATA_I6300ESB_R1 0x25b08086 #define ATA_I63XXESB2 0x269e8086 #define ATA_I63XXESB2_S1 0x26808086 -#define ATA_I63XXESB2_S2 0x26818086 -#define ATA_I63XXESB2_R1 0x26828086 -#define ATA_I63XXESB2_R2 0x26838086 #define ATA_I82801FB 0x266f8086 #define ATA_I82801FB_S1 0x26518086 #define ATA_I82801FB_R1 0x26528086 #define ATA_I82801FBM 0x26538086 #define ATA_I82801GB 0x27df8086 #define ATA_I82801GB_S1 0x27c08086 -#define ATA_I82801GB_AH 0x27c18086 -#define ATA_I82801GB_R1 0x27c38086 #define ATA_I82801GBM_S1 0x27c48086 -#define ATA_I82801GBM_AH 0x27c58086 -#define ATA_I82801GBM_R1 0x27c68086 #define ATA_I82801HB_S1 0x28208086 -#define ATA_I82801HB_AH6 0x28218086 -#define ATA_I82801HB_R1 0x28228086 -#define ATA_I82801HB_AH4 0x28248086 #define ATA_I82801HB_S2 0x28258086 #define ATA_I82801HBM 0x28508086 #define ATA_I82801HBM_S1 0x28288086 -#define ATA_I82801HBM_S2 0x28298086 -#define ATA_I82801HBM_S3 0x282a8086 #define ATA_I82801IB_S1 0x29208086 #define ATA_I82801IB_S3 0x29218086 -#define ATA_I82801IB_AH6 0x29228086 -#define ATA_I82801IB_AH4 0x29238086 #define ATA_I82801IB_R1 0x29258086 #define ATA_I82801IB_S2 0x29268086 #define ATA_I82801IBM_S1 0x29288086 -#define ATA_I82801IBM_AH 0x29298086 -#define ATA_I82801IBM_R1 0x292a8086 #define ATA_I82801IBM_S2 0x292d8086 #define ATA_I82801JIB_S1 0x3a208086 -#define ATA_I82801JIB_AH 0x3a228086 -#define ATA_I82801JIB_R1 0x3a258086 #define ATA_I82801JIB_S2 0x3a268086 #define ATA_I82801JD_S1 0x3a008086 -#define ATA_I82801JD_AH 0x3a028086 -#define ATA_I82801JD_R1 0x3a058086 #define ATA_I82801JD_S2 0x3a068086 #define ATA_I82801JI_S1 0x3a208086 -#define ATA_I82801JI_AH 0x3a228086 -#define ATA_I82801JI_R1 0x3a258086 #define ATA_I82801JI_S2 0x3a268086 #define ATA_5Series_S1 0x3b208086 #define ATA_5Series_S2 0x3b218086 -#define ATA_5Series_AH1 0x3b228086 -#define ATA_5Series_AH2 0x3b238086 -#define ATA_5Series_R1 0x3b258086 #define ATA_5Series_S3 0x3b268086 #define ATA_5Series_S4 0x3b288086 -#define ATA_5Series_AH3 0x3b298086 -#define ATA_5Series_R2 0x3b2c8086 #define ATA_5Series_S5 0x3b2d8086 #define ATA_5Series_S6 0x3b2e8086 -#define ATA_5Series_AH4 0x3b2f8086 #define ATA_CPT_S1 0x1c008086 #define ATA_CPT_S2 0x1c018086 -#define ATA_CPT_AH1 0x1c028086 -#define ATA_CPT_AH2 0x1c038086 -#define ATA_CPT_R1 0x1c048086 -#define ATA_CPT_R2 0x1c058086 #define ATA_CPT_S3 0x1c088086 #define ATA_CPT_S4 0x1c098086 #define ATA_PBG_S1 0x1d008086 -#define ATA_PBG_AH1 0x1d028086 -#define ATA_PBG_R1 0x1d048086 -#define ATA_PBG_R2 0x1d068086 -#define ATA_PBG_R3 0x28268086 #define ATA_PBG_S2 0x1d088086 #define ATA_PPT_S1 0x1e008086 #define ATA_PPT_S2 0x1e018086 -#define ATA_PPT_AH1 0x1e028086 -#define ATA_PPT_AH2 0x1e038086 -#define ATA_PPT_R1 0x1e048086 -#define ATA_PPT_R2 0x1e058086 -#define ATA_PPT_R3 0x1e068086 -#define ATA_PPT_R4 0x1e078086 #define ATA_PPT_S3 0x1e088086 #define ATA_PPT_S4 0x1e098086 -#define ATA_PPT_R5 0x1e0e8086 -#define ATA_PPT_R6 0x1e0f8086 #define ATA_AVOTON_S1 0x1f208086 #define ATA_AVOTON_S2 0x1f218086 @@ -264,29 +220,13 @@ struct ata_pci_controller { #define ATA_LPT_S1 0x8c008086 #define ATA_LPT_S2 0x8c018086 -#define ATA_LPT_AH1 0x8c028086 -#define ATA_LPT_AH2 0x8c038086 -#define ATA_LPT_R1 0x8c048086 -#define ATA_LPT_R2 0x8c058086 -#define ATA_LPT_R3 0x8c068086 -#define ATA_LPT_R4 0x8c078086 #define ATA_LPT_S3 0x8c088086 #define ATA_LPT_S4 0x8c098086 -#define ATA_LPT_R5 0x8c0e8086 -#define ATA_LPT_R6 0x8c0f8086 #define ATA_WCPT_S1 0x8c808086 #define ATA_WCPT_S2 0x8c818086 -#define ATA_WCPT_AH1 0x8c828086 -#define ATA_WCPT_AH2 0x8c838086 -#define ATA_WCPT_R1 0x8c848086 -#define ATA_WCPT_R2 0x8c858086 -#define ATA_WCPT_R3 0x8c868086 -#define ATA_WCPT_R4 0x8c878086 #define ATA_WCPT_S3 0x8c888086 #define ATA_WCPT_S4 0x8c898086 -#define ATA_WCPT_R5 0x8c8e8086 -#define ATA_WCPT_R6 0x8c8f8086 #define ATA_WELLS_S1 0x8d008086 #define ATA_WELLS_S2 0x8d088086 @@ -300,9 +240,7 @@ struct ata_pci_controller { #define ATA_I31244 0x32008086 #define ATA_ISCH 0x811a8086 -#define ATA_DH89XXCC 0x23238086 -#define ATA_COLETOCRK_AH1 0x23a38086 #define ATA_COLETOCRK_S1 0x23a18086 #define ATA_COLETOCRK_S2 0x23a68086 @@ -322,14 +260,6 @@ struct ata_pci_controller { #define ATA_JMB368_2 0x0368197b #define ATA_MARVELL_ID 0x11ab -#define ATA_M88SX5040 0x504011ab -#define ATA_M88SX5041 0x504111ab -#define ATA_M88SX5080 0x508011ab -#define ATA_M88SX5081 0x508111ab -#define ATA_M88SX6041 0x604111ab -#define ATA_M88SX6042 0x604211ab -#define ATA_M88SX6081 0x608111ab -#define ATA_M88SX7042 0x704211ab #define ATA_M88SE6101 0x610111ab #define ATA_M88SE6102 0x610211ab #define ATA_M88SE6111 0x611111ab @@ -505,10 +435,6 @@ struct ata_pci_controller { #define ATA_SII3512 0x35121095 #define ATA_SII3112 0x31121095 #define ATA_SII3112_1 0x02401095 -#define ATA_SII3124 0x31241095 -#define ATA_SII3132 0x31321095 -#define ATA_SII3132_1 0x02421095 -#define ATA_SII3132_2 0x02441095 #define ATA_SII0680 0x06801095 #define ATA_CMD646 0x06461095 #define ATA_CMD648 0x06481095 @@ -631,8 +557,6 @@ const struct ata_chip_id *ata_find_chip( int ata_mode2idx(int mode); /* global prototypes from chipsets/ata-*.c */ -int ata_ahci_chipinit(device_t); -int ata_marvell_edma_chipinit(device_t); int ata_sii_chipinit(device_t); /* externs */ Modified: stable/10/sys/dev/ata/chipsets/ata-acerlabs.c ============================================================================== --- stable/10/sys/dev/ata/chipsets/ata-acerlabs.c Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/chipsets/ata-acerlabs.c Sat Aug 22 07:32:47 2015 (r287016) @@ -117,11 +117,6 @@ ata_ali_chipinit(device_t dev) ctlr->setmode = ata_sata_setmode; ctlr->getrev = ata_sata_getrev; - /* AHCI mode is correctly supported only on the ALi 5288. */ - if ((ctlr->chip->chipid == ATA_ALI_5288) && - (ata_ahci_chipinit(dev) != ENXIO)) - return 0; - /* Allocate resources for later use by channel attach routines. */ res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK); for (i = 0; i < 4; i++) { @@ -347,4 +342,3 @@ ata_ali_setmode(device_t dev, int target } ATA_DECLARE_DRIVER(ata_ali); -MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1); Modified: stable/10/sys/dev/ata/chipsets/ata-ati.c ============================================================================== --- stable/10/sys/dev/ata/chipsets/ata-ati.c Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/chipsets/ata-ati.c Sat Aug 22 07:32:47 2015 (r287016) @@ -64,9 +64,6 @@ static int ata_ati_setmode(device_t dev, #define ATI_PATA 0x02 #define ATI_AHCI 0x04 -static int force_ahci = 1; -TUNABLE_INT("hw.ahci.force", &force_ahci); - /* * ATI chipset support functions */ @@ -104,8 +101,6 @@ ata_ati_probe(device_t dev) if (!(ctlr->chip = ata_match_chip(dev, ids))) return ENXIO; - ata_set_desc(dev); - switch (ctlr->chip->cfg1) { case ATI_PATA: ctlr->chipinit = ata_ati_chipinit; @@ -117,12 +112,13 @@ ata_ati_probe(device_t dev) ctlr->chipinit = ata_sii_chipinit; break; case ATI_AHCI: - if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE) - ctlr->chipinit = ata_ahci_chipinit; - else - ctlr->chipinit = ata_ati_chipinit; + if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) + return (ENXIO); + ctlr->chipinit = ata_ati_chipinit; break; } + + ata_set_desc(dev); return (BUS_PROBE_LOW_PRIORITY); } @@ -264,5 +260,4 @@ ata_ati_setmode(device_t dev, int target } ATA_DECLARE_DRIVER(ata_ati); -MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1); MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); Modified: stable/10/sys/dev/ata/chipsets/ata-intel.c ============================================================================== --- stable/10/sys/dev/ata/chipsets/ata-intel.c Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/chipsets/ata-intel.c Sat Aug 22 07:32:47 2015 (r287016) @@ -80,7 +80,6 @@ static void ata_intel_31244_tf_write(str static void ata_intel_31244_reset(device_t dev); /* misc defines */ -#define INTEL_AHCI 1 #define INTEL_ICH5 2 #define INTEL_6CH 4 #define INTEL_6CH2 8 @@ -127,118 +126,57 @@ ata_intel_probe(device_t dev) { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, - { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, - { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, - { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, + { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" }, + { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" }, + { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" }, { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, - { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, - { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, - { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, - { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, - { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, - { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, - { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, - { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, - { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, - { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, - { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, - { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, - { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, - { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, - { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, - { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, - { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, - { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, - { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, - { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, - { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, - { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, - { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, @@ -249,10 +187,8 @@ ata_intel_probe(device_t dev) { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, - { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, - { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" }, { 0, 0, 0, 0, 0, 0}}; if (pci_get_vendor(dev) != ATA_INTEL_ID) @@ -326,15 +262,6 @@ ata_intel_chipinit(device_t dev) ctlr->ch_detach = ata_pci_ch_detach; ctlr->reset = ata_intel_reset; - /* - * if we have AHCI capability and AHCI or RAID mode enabled - * in BIOS we try for AHCI mode - */ - if ((ctlr->chip->cfg1 & INTEL_AHCI) && - (pci_read_config(dev, 0x90, 1) & 0xc0) && - (ata_ahci_chipinit(dev) != ENXIO)) - return 0; - /* BAR(5) may point to SATA interface registers */ if ((ctlr->chip->cfg1 & INTEL_ICH7)) { ctlr->r_type2 = SYS_RES_MEMORY; @@ -995,4 +922,3 @@ ata_intel_31244_reset(device_t dev) } ATA_DECLARE_DRIVER(ata_intel); -MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); Modified: stable/10/sys/dev/ata/chipsets/ata-jmicron.c ============================================================================== --- stable/10/sys/dev/ata/chipsets/ata-jmicron.c Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/chipsets/ata-jmicron.c Sat Aug 22 07:32:47 2015 (r287016) @@ -100,11 +100,7 @@ ata_jmicron_chipinit(device_t dev) /* do we have multiple PCI functions ? */ if (pci_read_config(dev, 0xdf, 1) & 0x40) { - /* are we on the AHCI part ? */ - if (ata_ahci_chipinit(dev) != ENXIO) - return 0; - - /* otherwise we are on the PATA part */ + /* If this was not claimed by AHCI, then we are on the PATA part */ ctlr->ch_attach = ata_jmicron_ch_attach; ctlr->ch_detach = ata_pci_ch_detach; ctlr->reset = ata_generic_reset; @@ -160,4 +156,3 @@ ata_jmicron_setmode(device_t dev, int ta } ATA_DECLARE_DRIVER(ata_jmicron); -MODULE_DEPEND(ata_jmicron, ata_ahci, 1, 1, 1); Modified: stable/10/sys/dev/ata/chipsets/ata-marvell.c ============================================================================== --- stable/10/sys/dev/ata/chipsets/ata-marvell.c Sat Aug 22 07:27:06 2015 (r287015) +++ stable/10/sys/dev/ata/chipsets/ata-marvell.c Sat Aug 22 07:32:47 2015 (r287016) @@ -55,20 +55,8 @@ static int ata_marvell_chipinit(device_t static int ata_marvell_ch_attach(device_t dev); static int ata_marvell_setmode(device_t dev, int target, int mode); static int ata_marvell_dummy_chipinit(device_t dev); -static int ata_marvell_edma_ch_attach(device_t dev); -static int ata_marvell_edma_ch_detach(device_t dev); -static int ata_marvell_edma_status(device_t dev); -static int ata_marvell_edma_begin_transaction(struct ata_request *request); -static int ata_marvell_edma_end_transaction(struct ata_request *request); -static void ata_marvell_edma_reset(device_t dev); -static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); -static void ata_marvell_edma_dmainit(device_t dev); /* misc defines */ -#define MV_50XX 50 -#define MV_60XX 60 -#define MV_6042 62 -#define MV_7042 72 #define MV_61XX 61 #define MV_91XX 91 @@ -99,15 +87,7 @@ ata_marvell_probe(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); static const struct ata_chip_id ids[] = - {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" }, - { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" }, - { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" }, - { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" }, - { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" }, - { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" }, - { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" }, - { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" }, - { ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" }, + {{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" }, { ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" }, { ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" }, { ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" }, @@ -126,12 +106,6 @@ ata_marvell_probe(device_t dev) ata_set_desc(dev); switch (ctlr->chip->cfg2) { - case MV_50XX: - case MV_60XX: - case MV_6042: - case MV_7042: - ctlr->chipinit = ata_marvell_edma_chipinit; - break; case MV_61XX: ctlr->chipinit = ata_marvell_chipinit; break; @@ -205,425 +179,4 @@ ata_marvell_dummy_chipinit(device_t dev) return (0); } -int -ata_marvell_edma_chipinit(device_t dev) -{ - struct ata_pci_controller *ctlr = device_get_softc(dev); - - if (ata_setup_interrupt(dev, ata_generic_intr)) - return ENXIO; - - ctlr->r_type1 = SYS_RES_MEMORY; - ctlr->r_rid1 = PCIR_BAR(0); - if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, - &ctlr->r_rid1, RF_ACTIVE))) - return ENXIO; - - /* mask all host controller interrupts */ - ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); - - /* mask all PCI interrupts */ - ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); - - ctlr->ch_attach = ata_marvell_edma_ch_attach; - ctlr->ch_detach = ata_marvell_edma_ch_detach; - ctlr->reset = ata_marvell_edma_reset; - ctlr->setmode = ata_sata_setmode; - ctlr->getrev = ata_sata_getrev; - ctlr->channels = ctlr->chip->cfg1; - - /* clear host controller interrupts */ - ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); - if (ctlr->chip->cfg1 > 4) - ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); - - /* clear PCI interrupts */ - ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); - - /* unmask PCI interrupts we want */ - ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); - - /* unmask host controller interrupts we want */ - ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | - /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); - - return 0; -} - -static int -ata_marvell_edma_ch_attach(device_t dev) -{ - struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); - struct ata_channel *ch = device_get_softc(dev); - u_int64_t work; - int i; - - ata_marvell_edma_dmainit(dev); - work = ch->dma.work_bus; - /* clear work area */ - bzero(ch->dma.work, 1024+256); - bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - /* set legacy ATA resources */ - for (i = ATA_DATA; i <= ATA_COMMAND; i++) { - ch->r_io[i].res = ctlr->r_res1; - ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); - } - ch->r_io[ATA_CONTROL].res = ctlr->r_res1; - ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); - ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; - ata_default_registers(dev); - - /* set SATA resources */ - switch (ctlr->chip->cfg2) { - case MV_50XX: - ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; - ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); - ch->r_io[ATA_SERROR].res = ctlr->r_res1; - ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); - ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; - ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); - break; - case MV_60XX: - case MV_6042: - case MV_7042: - ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; - ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); - ch->r_io[ATA_SERROR].res = ctlr->r_res1; - ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); - ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; - ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); - ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; - ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); - break; - } - - ch->flags |= ATA_NO_SLAVE; - ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ - ch->flags |= ATA_SATA; - ata_generic_hw(dev); - ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; - ch->hw.end_transaction = ata_marvell_edma_end_transaction; - ch->hw.status = ata_marvell_edma_status; - - /* disable the EDMA machinery */ - ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); - DELAY(100000); /* SOS should poll for disabled */ - - /* set configuration to non-queued 128b read transfers stop on error */ - ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); - - /* request queue base high */ - ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); - - /* request queue in ptr */ - ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); - - /* request queue out ptr */ - ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); - - /* response queue base high */ - work += 1024; - ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); - - /* response queue in ptr */ - ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); - - /* response queue out ptr */ - ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); - - /* clear SATA error register */ - ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); - - /* clear any outstanding error interrupts */ - ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); - - /* unmask all error interrupts */ - ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); - - /* enable EDMA machinery */ - ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); - return 0; -} - -static int -ata_marvell_edma_ch_detach(device_t dev) -{ - struct ata_channel *ch = device_get_softc(dev); - - if (ch->dma.work_tag && ch->dma.work_map) - bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - ata_dmafini(dev); - return (0); -} - *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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