Date: Wed, 28 Nov 2018 09:22:42 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341122 - head/sys/dev/sfxge/common Message-ID: <201811280922.wAS9MgH8061812@repo.freebsd.org>
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Author: arybchik Date: Wed Nov 28 09:22:42 2018 New Revision: 341122 URL: https://svnweb.freebsd.org/changeset/base/341122 Log: sfxge(4): support FEC mode settings Medford2 controllers support control and reporting of FEC modes for 25G and higher links. See SF-109306-TC for suggested usage in client code. Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18197 Modified: head/sys/dev/sfxge/common/ef10_phy.c head/sys/dev/sfxge/common/efx.h Modified: head/sys/dev/sfxge/common/ef10_phy.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_phy.c Wed Nov 28 09:10:28 2018 (r341121) +++ head/sys/dev/sfxge/common/ef10_phy.c Wed Nov 28 09:22:42 2018 (r341122) @@ -61,6 +61,12 @@ mcdi_phy_decode_cap( CHECK_CAP(ASYM); CHECK_CAP(AN); CHECK_CAP(DDM); + CHECK_CAP(BASER_FEC); + CHECK_CAP(BASER_FEC_REQUESTED); + CHECK_CAP(RS_FEC); + CHECK_CAP(RS_FEC_REQUESTED); + CHECK_CAP(25G_BASER_FEC); + CHECK_CAP(25G_BASER_FEC_REQUESTED); #undef CHECK_CAP mask = 0; @@ -94,6 +100,22 @@ mcdi_phy_decode_cap( if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) mask |= (1 << EFX_PHY_CAP_AN); + /* FEC caps (supported on Medford2 and later) */ + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN)) + mask |= (1 << EFX_PHY_CAP_BASER_FEC); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN)) + mask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED); + + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN)) + mask |= (1 << EFX_PHY_CAP_RS_FEC); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN)) + mask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED); + + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN)) + mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC); + if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN)) + mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); + *maskp = mask; } @@ -349,6 +371,25 @@ ef10_phy_reconfigure( PHY_CAP_50000FDX, (cap_mask >> EFX_PHY_CAP_50000FDX) & 0x1); MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1); + + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1); + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_BASER_FEC_REQUESTED, + (cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1); + + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1); + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_RS_FEC_REQUESTED, + (cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1); + + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_25G_BASER_FEC, + (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1); + MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP, + PHY_CAP_25G_BASER_FEC_REQUESTED, + (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1); #if EFSYS_OPT_LOOPBACK MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, Modified: head/sys/dev/sfxge/common/efx.h ============================================================================== --- head/sys/dev/sfxge/common/efx.h Wed Nov 28 09:10:28 2018 (r341121) +++ head/sys/dev/sfxge/common/efx.h Wed Nov 28 09:22:42 2018 (r341122) @@ -904,6 +904,12 @@ typedef enum efx_phy_cap_type_e { EFX_PHY_CAP_100000FDX, EFX_PHY_CAP_25000FDX, EFX_PHY_CAP_50000FDX, + EFX_PHY_CAP_BASER_FEC, + EFX_PHY_CAP_BASER_FEC_REQUESTED, + EFX_PHY_CAP_RS_FEC, + EFX_PHY_CAP_RS_FEC_REQUESTED, + EFX_PHY_CAP_25G_BASER_FEC, + EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, EFX_PHY_CAP_NTYPES } efx_phy_cap_type_t;
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