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Date:      Mon, 22 Mar 1999 12:04:04 -0800
From:      Mike Smith <mike@smith.net.au>
To:        Dennis <dennis@etinc.com>
Cc:        Mike Smith <mike@smith.net.au>, Amancio Hasty <hasty@rah.star-gate.com>, hackers@freebsd.org
Subject:   Re: Gigabit ethernet -- what am I doing wrong? 
Message-ID:  <199903222004.MAA00488@dingo.cdrom.com>
In-Reply-To: Your message of "Mon, 22 Mar 1999 12:07:02 EST." <199903221711.MAA20551@etinc.com> 

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> >> And as far a 64 bit busses.....there
> >> arent many
> >> processors that can do is, and doubling the bandwidth on a 32bit processor
> >> isnt
> >> always linear in performance. You have to get a whole new generation of 
> >> processors before you will see any usable products.
> >
> >This has nothing whatever to do with reality, however.  Most PCI 
> >peripherals are bus masters, and most memory busses these days are at 
> >least 64 bits wide, so 64 bit PCI has very real performance benefits.
> >
> >The processor's internal word size has little or nothing to do with the 
> >equation.
> 
> The ability to do single-cycle transfers IS affected by the internal
> processor's
> word size. If it can't do sustained single-cycle bursts then performance
> suffers
> significantly, so I disagree wholeheartedly on this. If the on-board processor
> doesnt  have a 64bit bus it is very difficult to do single cycle transfers.

Uh, I don't know what version of PCI you've been using up 'till now, 
but busmaster DMA transactions (the only way to get performace out of 
PCI at all) do not in any way shape or form involve the CPU.

In addition, single-cycle burst transactions are so hopelessly 
inefficient (they are only useful for PIO) that, again, they have no 
place whatsoever in this discussion.

-- 
\\  Sometimes you're ahead,       \\  Mike Smith
\\  sometimes you're behind.      \\  mike@smith.net.au
\\  The race is long, and in the  \\  msmith@freebsd.org
\\  end it's only with yourself.  \\  msmith@cdrom.com




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