Date: Mon, 21 Nov 2005 19:15:07 GMT From: Olivier Houchard <cognet@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 87032 for review Message-ID: <200511211915.jALJF7pH066221@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=87032 Change 87032 by cognet@cognet on 2005/11/21 19:14:53 Bring in more AT91RM92 bits. It now goes to the point where it asks for the root partition, and only needs a real UART driver to go single user. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/at91rm92.c#4 edit .. //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#4 edit .. //depot/projects/arm/src/sys/arm/at91/at91rm92timer.c#2 edit .. //depot/projects/arm/src/sys/arm/at91/files.at91rm92#2 edit .. //depot/projects/arm/src/sys/arm/at91/files.kb920x#2 edit .. //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c#2 edit .. //depot/projects/arm/src/sys/arm/at91/uart_bus_at91rm92usart.c#1 add .. //depot/projects/arm/src/sys/arm/at91/uart_cpu_at91rm92usart.c#1 add .. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91rm92usart.c#1 add .. //depot/projects/arm/src/sys/arm/conf/KB920X#2 edit .. //depot/projects/arm/src/sys/arm/conf/SKYEYE#1 add Differences ... ==== //depot/projects/arm/src/sys/arm/at91/at91rm92.c#4 (text+ko) ==== @@ -86,7 +86,7 @@ bs_protos(generic); bs_protos(generic_armv4); -static struct bus_space at91rm92_bs_tag = { +struct bus_space at91rm92_bs_tag = { /* cookie */ (void *) 0, @@ -226,6 +226,7 @@ device_add_child(dev, "at91rm92_timer", 0); bus_generic_probe(dev); bus_generic_attach(dev); + enable_interrupts(I32_bit | F32_bit); return (0); } ==== //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#4 (text+ko) ==== @@ -55,11 +55,34 @@ #define AT91RM92_USART_SIZE 0x4000 #define USART_CR 0x00 /* Control register */ +#define USART_CR_RSTRX (1 << 2) /* Reset Receiver */ +#define USART_CR_RSTTX (1 << 3) /* Reset Transmitter */ +#define USART_CR_RXEN (1 << 4) /* Receiver Enable */ +#define USART_CR_RXDIS (1 << 5) /* Receiver Disable */ +#define USART_CR_TXEN (1 << 6) /* Transmitter Enable */ +#define USART_CR_TXDIS (1 << 7) /* Transmitter Disable */ +#define USART_CR_RSTSTA (1 << 8) /* Reset Status Bits */ +#define USART_CR_STTBRK (1 << 9) /* Start Break */ +#define USART_CR_STPBRK (1 << 10) /* Stop Break */ +#define USART_CR_STTTO (1 << 11) /* Start Time-out */ +#define USART_CR_SENDA (1 << 12) /* Send Address */ +#define USART_CR_RSTIT (1 << 13) /* Reset Iterations */ +#define USART_CR_RSTNACK (1 << 14) /* Reset Non Acknowledge */ +#define USART_CR_RETTO (1 << 15) /* Rearm Time-out */ +#define USART_CR_DTREN (1 << 16) /* Data Terminal ready Enable */ +#define USART_CR_DTRDIS (1 << 17) /* Data Terminal ready Disable */ +#define USART_CR_RTSEN (1 << 18) /* Request to Send enable */ +#define USART_CR_RTSDIS (1 << 19) /* Request to Send Disable */ + #define USART_MR 0x04 /* Mode register */ #define USART_IER 0x08 /* Interrupt enable register */ #define USART_IDR 0x0c /* Interrupt disable register */ #define USART_IMR 0x10 /* Interrupt mask register */ #define USART_CSR 0x14 /* Channel status register */ + +#define USART_CSR_RXRDY (1 << 0) /* Receiver ready */ +#define USART_CSR_TXRDY (1 << 1) /* Transmitter ready */ + #define USART_RHR 0x18 /* Receiver holding register */ #define USART_THR 0x1c /* Transmitter holding register */ #define USART_BRGR 0x20 /* Baud rate generator register */ @@ -96,166 +119,166 @@ #define AT91RM92_SYS_BASE 0xffff000 #define AT91RM92_SYS_SIZE 0x1000 /* Interrupt Controller */ -#define IC_SMR (AT91RM92_SYS_BASE) /* Source mode register */ -#define IC_SVR (AT91RM92_SYS_BASE + 128) /* Source vector register */ -#define IC_IVR (AT91RM92_SYS_BASE + 256) /* IRQ vector register */ -#define IC_FVR (AT91RM92_SYS_BASE + 260) /* FIQ vector register */ -#define IC_ISR (AT91RM92_SYS_BASE + 264) /* Interrupt status register */ -#define IC_IPR (AT91RM92_SYS_BASE + 268) /* Interrupt pending register */ -#define IC_IMR (AT91RM92_SYS_BASE + 272) /* Interrupt status register */ -#define IC_CISR (AT91RM92_SYS_BASE + 276) /* Core interrupt status register */ -#define IC_IECR (AT91RM92_SYS_BASE + 288) /* Interrupt enable command register */ -#define IC_IDCR (AT91RM92_SYS_BASE + 292) /* Interrupt disable command register */ -#define IC_ICCR (AT91RM92_SYS_BASE + 296) /* Interrupt clear command register */ -#define IC_ISCR (AT91RM92_SYS_BASE + 300) /* Interrupt set command register */ -#define IC_EOICR (AT91RM92_SYS_BASE + 304) /* End of interrupt command register */ -#define IC_SPU (AT91RM92_SYS_BASE + 308) /* Spurious vector register */ -#define IC_DCR (AT91RM92_SYS_BASE + 312) /* Debug control register */ -#define IC_FFER (AT91RM92_SYS_BASE + 320) /* Fast forcing enable register */ -#define IC_FFDR (AT91RM92_SYS_BASE + 324) /* Fast forcing disable register */ -#define IC_FFSR (AT91RM92_SYS_BASE + 328) /* Fast forcing status register */ +#define IC_SMR (0) /* Source mode register */ +#define IC_SVR (128) /* Source vector register */ +#define IC_IVR (256) /* IRQ vector register */ +#define IC_FVR (260) /* FIQ vector register */ +#define IC_ISR (264) /* Interrupt status register */ +#define IC_IPR (268) /* Interrupt pending register */ +#define IC_IMR (272) /* Interrupt status register */ +#define IC_CISR (276) /* Core interrupt status register */ +#define IC_IECR (288) /* Interrupt enable command register */ +#define IC_IDCR (292) /* Interrupt disable command register */ +#define IC_ICCR (296) /* Interrupt clear command register */ +#define IC_ISCR (300) /* Interrupt set command register */ +#define IC_EOICR (304) /* End of interrupt command register */ +#define IC_SPU (308) /* Spurious vector register */ +#define IC_DCR (312) /* Debug control register */ +#define IC_FFER (320) /* Fast forcing enable register */ +#define IC_FFDR (324) /* Fast forcing disable register */ +#define IC_FFSR (328) /* Fast forcing status register */ /* DBGU */ -#define DBGU_CR (AT91RM92_SYS_BASE + 0x200) /* Control register */ -#define DBGU_MR (AT91RM92_SYS_BASE + 0x200 + 4) /* Mode register */ -#define DBGU_IER (AT91RM92_SYS_BASE + 0x200 + 8) /* Interrupt Enable Register */ -#define DBGU_IDR (AT91RM92_SYS_BASE + 0x200 + 12) /* Interrupt Disable Register */ -#define DBGU_IMR (AT91RM92_SYS_BASE + 0x200 + 16) /* Interrupt Mask Register */ -#define DBGU_CSR (AT91RM92_SYS_BASE + 0x200 + 20) /* Channel Status Register */ -#define DBGU_RHR (AT91RM92_SYS_BASE + 0x200 + 24) /* Receiver Holding Register */ -#define DBGU_THR (AT91RM92_SYS_BASE + 0x200 + 28) /* Transmitter Holding Register */ -#define DBGU_BRGR (AT91RM92_SYS_BASE + 0x200 + 32) /* Baud Rate Generator Register */ -#define DBGU_C1R (AT91RM92_SYS_BASE + 0x200 + 64) /* Chip ID1 Register */ -#define DBGU_C2R (AT91RM92_SYS_BASE + 0x200 + 68) /* Chip ID2 Register */ -#define DBGU_FNTR (AT91RM92_SYS_BASE + 0x200 + 72) /* Force NTRST Register */ -#define DBGU_RPR (AT91RM92_SYS_BASE + 0x200 + 256) /* Receive Pointer Register */ -#define DBGU_RCR (AT91RM92_SYS_BASE + 0x200 + 260) /* Receive Counter Register */ -#define DBGU_TPR (AT91RM92_SYS_BASE + 0x200 + 264) /* Transmit Pointer Register */ -#define DBGU_TCR (AT91RM92_SYS_BASE + 0x200 + 268) /* Transmit Counter Register */ -#define DBGU_RNPR (AT91RM92_SYS_BASE + 0x200 + 272) /* Receive Next Pointer Register */ -#define DBGU_RNCR (AT91RM92_SYS_BASE + 0x200 + 276) /* Receive Next Counter Register */ -#define DBGU_TNPR (AT91RM92_SYS_BASE + 0x200 + 280) /* Transmit Next Pointer Register */ -#define DBGU_TNCR (AT91RM92_SYS_BASE + 0x200 + 284) /* Transmit Next Counter Register */ -#define DBGU_PTCR (AT91RM92_SYS_BASE + 0x200 + 288) /* PDC Transfer Control Register */ -#define DBGU_PTSR (AT91RM92_SYS_BASE + 0x200 + 292) /* PDC Transfer Status Register */ +#define DBGU_CR (0x200) /* Control register */ +#define DBGU_MR (0x200 + 4) /* Mode register */ +#define DBGU_IER (0x200 + 8) /* Interrupt Enable Register */ +#define DBGU_IDR (0x200 + 12) /* Interrupt Disable Register */ +#define DBGU_IMR (0x200 + 16) /* Interrupt Mask Register */ +#define DBGU_CSR (0x200 + 20) /* Channel Status Register */ +#define DBGU_RHR (0x200 + 24) /* Receiver Holding Register */ +#define DBGU_THR (0x200 + 28) /* Transmitter Holding Register */ +#define DBGU_BRGR (0x200 + 32) /* Baud Rate Generator Register */ +#define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */ +#define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */ +#define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */ +#define DBGU_RPR (0x200 + 256) /* Receive Pointer Register */ +#define DBGU_RCR (0x200 + 260) /* Receive Counter Register */ +#define DBGU_TPR (0x200 + 264) /* Transmit Pointer Register */ +#define DBGU_TCR (0x200 + 268) /* Transmit Counter Register */ +#define DBGU_RNPR (0x200 + 272) /* Receive Next Pointer Register */ +#define DBGU_RNCR (0x200 + 276) /* Receive Next Counter Register */ +#define DBGU_TNPR (0x200 + 280) /* Transmit Next Pointer Register */ +#define DBGU_TNCR (0x200 + 284) /* Transmit Next Counter Register */ +#define DBGU_PTCR (0x200 + 288) /* PDC Transfer Control Register */ +#define DBGU_PTSR (0x200 + 292) /* PDC Transfer Status Register */ -#define PIOA_PER (AT91RM92_SYS_BASE + 0x400) /* PIO Enable Register */ -#define PIOA_PDR (AT91RM92_SYS_BASE + 0x400 + 4) /* PIO Disable Register */ -#define PIOA_PSR (AT91RM92_SYS_BASE + 0x400 + 8) /* PIO status register */ -#define PIOA_OER (AT91RM92_SYS_BASE + 0x400 + 12) /* Output enable register */ -#define PIOA_ODR (AT91RM92_SYS_BASE + 0x400 + 20) /* Output disable register */ -#define PIOA_OSR (AT91RM92_SYS_BASE + 0x400 + 24) /* Output status register */ -#define PIOA_IFER (AT91RM92_SYS_BASE + 0x400 + 28) /* Input filter enable register */ -#define PIOA_IFDR (AT91RM92_SYS_BASE + 0x400 + 36) /* Input filter disable register */ -#define PIOA_IFSR (AT91RM92_SYS_BASE + 0x400 + 40) /* Input filter status register */ -#define PIOA_SODR (AT91RM92_SYS_BASE + 0x400 + 48) /* Set output data register */ -#define PIOA_CODR (AT91RM92_SYS_BASE + 0x400 + 52) /* Clear output data register */ -#define PIOA_ODSR (AT91RM92_SYS_BASE + 0x400 + 56) /* Output data status register */ -#define PIOA_PDSR (AT91RM92_SYS_BASE + 0x400 + 60) /* Pin data status register */ -#define PIOA_IER (AT91RM92_SYS_BASE + 0x400 + 64) /* Interrupt enable register */ -#define PIOA_IDR (AT91RM92_SYS_BASE + 0x400 + 68) /* Interrupt disable register */ -#define PIOA_IMR (AT91RM92_SYS_BASE + 0x400 + 72) /* Interrupt mask register */ -#define PIOA_ISR (AT91RM92_SYS_BASE + 0x400 + 76) /* Interrupt status register */ -#define PIOA_MDER (AT91RM92_SYS_BASE + 0x400 + 80) /* Multi driver enable register */ -#define PIOA_MDDR (AT91RM92_SYS_BASE + 0x400 + 84) /* Multi driver disable register */ -#define PIOA_MDSR (AT91RM92_SYS_BASE + 0x400 + 88) /* Multi driver status register */ -#define PIOA_PPUDR (AT91RM92_SYS_BASE + 0x400 + 96) /* Pull-up disable register */ -#define PIOA_PPUER (AT91RM92_SYS_BASE + 0x400 + 100) /* Pull-up enable register */ -#define PIOA_PPUSR (AT91RM92_SYS_BASE + 0x400 + 104) /* Pad pull-up status register */ -#define PIOA_ASR (AT91RM92_SYS_BASE + 0x400 + 112) /* Select A register */ -#define PIOA_BSR (AT91RM92_SYS_BASE + 0x400 + 116) /* Select B register */ -#define PIOA_ABSR (AT91RM92_SYS_BASE + 0x400 + 120) /* AB Select status register */ -#define PIOA_OWER (AT91RM92_SYS_BASE + 0x400 + 160) /* Output Write enable register */ -#define PIOA_OWDR (AT91RM92_SYS_BASE + 0x400 + 164) /* Output write disable register */ -#define PIOA_OWSR (AT91RM92_SYS_BASE + 0x400 + 168) /* Output write status register */ -#define PIOB_PER (AT91RM92_SYS_BASE + 0x400) /* PIO Enable Register */ -#define PIOB_PDR (AT91RM92_SYS_BASE + 0x600 + 4) /* PIO Disable Register */ -#define PIOB_PSR (AT91RM92_SYS_BASE + 0x600 + 8) /* PIO status register */ -#define PIOB_OER (AT91RM92_SYS_BASE + 0x600 + 12) /* Output enable register */ -#define PIOB_ODR (AT91RM92_SYS_BASE + 0x600 + 20) /* Output disable register */ -#define PIOB_OSR (AT91RM92_SYS_BASE + 0x600 + 24) /* Output status register */ -#define PIOB_IFER (AT91RM92_SYS_BASE + 0x600 + 28) /* Input filter enable register */ -#define PIOB_IFDR (AT91RM92_SYS_BASE + 0x600 + 36) /* Input filter disable register */ -#define PIOB_IFSR (AT91RM92_SYS_BASE + 0x600 + 40) /* Input filter status register */ -#define PIOB_SODR (AT91RM92_SYS_BASE + 0x600 + 48) /* Set output data register */ -#define PIOB_CODR (AT91RM92_SYS_BASE + 0x600 + 52) /* Clear output data register */ -#define PIOB_ODSR (AT91RM92_SYS_BASE + 0x600 + 56) /* Output data status register */ -#define PIOB_PDSR (AT91RM92_SYS_BASE + 0x600 + 60) /* Pin data status register */ -#define PIOB_IER (AT91RM92_SYS_BASE + 0x600 + 64) /* Interrupt enable register */ -#define PIOB_IDR (AT91RM92_SYS_BASE + 0x600 + 68) /* Interrupt disable register */ -#define PIOB_IMR (AT91RM92_SYS_BASE + 0x600 + 72) /* Interrupt mask register */ -#define PIOB_ISR (AT91RM92_SYS_BASE + 0x600 + 76) /* Interrupt status register */ -#define PIOB_MDER (AT91RM92_SYS_BASE + 0x600 + 80) /* Multi driver enable register */ -#define PIOB_MDDR (AT91RM92_SYS_BASE + 0x600 + 84) /* Multi driver disable register */ -#define PIOB_MDSR (AT91RM92_SYS_BASE + 0x600 + 88) /* Multi driver status register */ -#define PIOB_PPUDR (AT91RM92_SYS_BASE + 0x600 + 96) /* Pull-up disable register */ -#define PIOB_PPUER (AT91RM92_SYS_BASE + 0x600 + 100) /* Pull-up enable register */ -#define PIOB_PPUSR (AT91RM92_SYS_BASE + 0x600 + 104) /* Pad pull-up status register */ -#define PIOB_ASR (AT91RM92_SYS_BASE + 0x600 + 112) /* Select A register */ -#define PIOB_BSR (AT91RM92_SYS_BASE + 0x600 + 116) /* Select B register */ -#define PIOB_ABSR (AT91RM92_SYS_BASE + 0x600 + 120) /* AB Select status register */ -#define PIOB_OWER (AT91RM92_SYS_BASE + 0x600 + 160) /* Output Write enable register */ -#define PIOB_OWDR (AT91RM92_SYS_BASE + 0x600 + 164) /* Output write disable register */ -#define PIOB_OWSR (AT91RM92_SYS_BASE + 0x600 + 168) /* Output write status register */ -#define PIOC_PER (AT91RM92_SYS_BASE + 0x800) /* PIO Enable Register */ -#define PIOC_PDR (AT91RM92_SYS_BASE + 0x800 + 4) /* PIO Disable Register */ -#define PIOC_PSR (AT91RM92_SYS_BASE + 0x800 + 8) /* PIO status register */ -#define PIOC_OER (AT91RM92_SYS_BASE + 0x800 + 12) /* Output enable register */ -#define PIOC_ODR (AT91RM92_SYS_BASE + 0x800 + 20) /* Output disable register */ -#define PIOC_OSR (AT91RM92_SYS_BASE + 0x800 + 24) /* Output status register */ -#define PIOC_IFER (AT91RM92_SYS_BASE + 0x800 + 28) /* Input filter enable register */ -#define PIOC_IFDR (AT91RM92_SYS_BASE + 0x800 + 36) /* Input filter disable register */ -#define PIOC_IFSR (AT91RM92_SYS_BASE + 0x800 + 40) /* Input filter status register */ -#define PIOC_SODR (AT91RM92_SYS_BASE + 0x800 + 48) /* Set output data register */ -#define PIOC_CODR (AT91RM92_SYS_BASE + 0x800 + 52) /* Clear output data register */ -#define PIOC_ODSR (AT91RM92_SYS_BASE + 0x800 + 56) /* Output data status register */ -#define PIOC_PDSR (AT91RM92_SYS_BASE + 0x800 + 60) /* Pin data status register */ -#define PIOC_IER (AT91RM92_SYS_BASE + 0x800 + 64) /* Interrupt enable register */ -#define PIOC_IDR (AT91RM92_SYS_BASE + 0x800 + 68) /* Interrupt disable register */ -#define PIOC_IMR (AT91RM92_SYS_BASE + 0x800 + 72) /* Interrupt mask register */ -#define PIOC_ISR (AT91RM92_SYS_BASE + 0x800 + 76) /* Interrupt status register */ -#define PIOC_MDER (AT91RM92_SYS_BASE + 0x800 + 80) /* Multi driver enable register */ -#define PIOC_MDDR (AT91RM92_SYS_BASE + 0x800 + 84) /* Multi driver disable register */ -#define PIOC_MDSR (AT91RM92_SYS_BASE + 0x800 + 88) /* Multi driver status register */ -#define PIOC_PPUDR (AT91RM92_SYS_BASE + 0x800 + 96) /* Pull-up disable register */ -#define PIOC_PPUER (AT91RM92_SYS_BASE + 0x800 + 100) /* Pull-up enable register */ -#define PIOC_PPUSR (AT91RM92_SYS_BASE + 0x800 + 104) /* Pad pull-up status register */ -#define PIOC_ASR (AT91RM92_SYS_BASE + 0x800 + 112) /* Select A register */ -#define PIOC_BSR (AT91RM92_SYS_BASE + 0x800 + 116) /* Select B register */ -#define PIOC_ABSR (AT91RM92_SYS_BASE + 0x800 + 120) /* AB Select status register */ -#define PIOC_OWER (AT91RM92_SYS_BASE + 0x800 + 160) /* Output Write enable register */ -#define PIOC_OWDR (AT91RM92_SYS_BASE + 0x800 + 164) /* Output write disable register */ -#define PIOC_OWSR (AT91RM92_SYS_BASE + 0x800 + 168) /* Output write status register */ -#define PIOD_PER (AT91RM92_SYS_BASE + 0xa00) /* PIO Enable Register */ -#define PIOD_PDR (AT91RM92_SYS_BASE + 0xa00 + 4) /* PIO Disable Register */ -#define PIOD_PSR (AT91RM92_SYS_BASE + 0xa00 + 8) /* PIO status register */ -#define PIOD_OER (AT91RM92_SYS_BASE + 0xa00 + 12) /* Output enable register */ -#define PIOD_ODR (AT91RM92_SYS_BASE + 0xa00 + 20) /* Output disable register */ -#define PIOD_OSR (AT91RM92_SYS_BASE + 0xa00 + 24) /* Output status register */ -#define PIOD_IFER (AT91RM92_SYS_BASE + 0xa00 + 28) /* Input filter enable register */ -#define PIOD_IFDR (AT91RM92_SYS_BASE + 0xa00 + 36) /* Input filter disable register */ -#define PIOD_IFSR (AT91RM92_SYS_BASE + 0xa00 + 40) /* Input filter status register */ -#define PIOD_SODR (AT91RM92_SYS_BASE + 0xa00 + 48) /* Set output data register */ -#define PIOD_CODR (AT91RM92_SYS_BASE + 0xa00 + 52) /* Clear output data register */ -#define PIOD_ODSR (AT91RM92_SYS_BASE + 0xa00 + 56) /* Output data status register */ -#define PIOD_PDSR (AT91RM92_SYS_BASE + 0xa00 + 60) /* Pin data status register */ -#define PIOD_IER (AT91RM92_SYS_BASE + 0xa00 + 64) /* Interrupt enable register */ -#define PIOD_IDR (AT91RM92_SYS_BASE + 0xa00 + 68) /* Interrupt disable register */ -#define PIOD_IMR (AT91RM92_SYS_BASE + 0xa00 + 72) /* Interrupt mask register */ -#define PIOD_ISR (AT91RM92_SYS_BASE + 0xa00 + 76) /* Interrupt status register */ -#define PIOD_MDER (AT91RM92_SYS_BASE + 0xa00 + 80) /* Multi driver enable register */ -#define PIOD_MDDR (AT91RM92_SYS_BASE + 0xa00 + 84) /* Multi driver disable register */ -#define PIOD_MDSR (AT91RM92_SYS_BASE + 0xa00 + 88) /* Multi driver status register */ -#define PIOD_PPUDR (AT91RM92_SYS_BASE + 0xa00 + 96) /* Pull-up disable register */ -#define PIOD_PPUER (AT91RM92_SYS_BASE + 0xa00 + 100) /* Pull-up enable register */ -#define PIOD_PPUSR (AT91RM92_SYS_BASE + 0xa00 + 104) /* Pad pull-up status register */ -#define PIOD_ASR (AT91RM92_SYS_BASE + 0xa00 + 112) /* Select A register */ -#define PIOD_BSR (AT91RM92_SYS_BASE + 0xa00 + 116) /* Select B register */ -#define PIOD_ABSR (AT91RM92_SYS_BASE + 0xa00 + 120) /* AB Select status register */ -#define PIOD_OWER (AT91RM92_SYS_BASE + 0xa00 + 160) /* Output Write enable register */ -#define PIOD_OWDR (AT91RM92_SYS_BASE + 0xa00 + 164) /* Output write disable register */ -#define PIOD_OWSR (AT91RM92_SYS_BASE + 0xa00 + 168) /* Output write status register */ +#define PIOA_PER (0x400) /* PIO Enable Register */ +#define PIOA_PDR (0x400 + 4) /* PIO Disable Register */ +#define PIOA_PSR (0x400 + 8) /* PIO status register */ +#define PIOA_OER (0x400 + 12) /* Output enable register */ +#define PIOA_ODR (0x400 + 20) /* Output disable register */ +#define PIOA_OSR (0x400 + 24) /* Output status register */ +#define PIOA_IFER (0x400 + 28) /* Input filter enable register */ +#define PIOA_IFDR (0x400 + 36) /* Input filter disable register */ +#define PIOA_IFSR (0x400 + 40) /* Input filter status register */ +#define PIOA_SODR (0x400 + 48) /* Set output data register */ +#define PIOA_CODR (0x400 + 52) /* Clear output data register */ +#define PIOA_ODSR (0x400 + 56) /* Output data status register */ +#define PIOA_PDSR (0x400 + 60) /* Pin data status register */ +#define PIOA_IER (0x400 + 64) /* Interrupt enable register */ +#define PIOA_IDR (0x400 + 68) /* Interrupt disable register */ +#define PIOA_IMR (0x400 + 72) /* Interrupt mask register */ +#define PIOA_ISR (0x400 + 76) /* Interrupt status register */ +#define PIOA_MDER (0x400 + 80) /* Multi driver enable register */ +#define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */ +#define PIOA_MDSR (0x400 + 88) /* Multi driver status register */ +#define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */ +#define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */ +#define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */ +#define PIOA_ASR (0x400 + 112) /* Select A register */ +#define PIOA_BSR (0x400 + 116) /* Select B register */ +#define PIOA_ABSR (0x400 + 120) /* AB Select status register */ +#define PIOA_OWER (0x400 + 160) /* Output Write enable register */ +#define PIOA_OWDR (0x400 + 164) /* Output write disable register */ +#define PIOA_OWSR (0x400 + 168) /* Output write status register */ +#define PIOB_PER (0x400) /* PIO Enable Register */ +#define PIOB_PDR (0x600 + 4) /* PIO Disable Register */ +#define PIOB_PSR (0x600 + 8) /* PIO status register */ +#define PIOB_OER (0x600 + 12) /* Output enable register */ +#define PIOB_ODR (0x600 + 20) /* Output disable register */ +#define PIOB_OSR (0x600 + 24) /* Output status register */ +#define PIOB_IFER (0x600 + 28) /* Input filter enable register */ +#define PIOB_IFDR (0x600 + 36) /* Input filter disable register */ +#define PIOB_IFSR (0x600 + 40) /* Input filter status register */ +#define PIOB_SODR (0x600 + 48) /* Set output data register */ +#define PIOB_CODR (0x600 + 52) /* Clear output data register */ +#define PIOB_ODSR (0x600 + 56) /* Output data status register */ +#define PIOB_PDSR (0x600 + 60) /* Pin data status register */ +#define PIOB_IER (0x600 + 64) /* Interrupt enable register */ +#define PIOB_IDR (0x600 + 68) /* Interrupt disable register */ +#define PIOB_IMR (0x600 + 72) /* Interrupt mask register */ +#define PIOB_ISR (0x600 + 76) /* Interrupt status register */ +#define PIOB_MDER (0x600 + 80) /* Multi driver enable register */ +#define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */ +#define PIOB_MDSR (0x600 + 88) /* Multi driver status register */ +#define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */ +#define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */ +#define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */ +#define PIOB_ASR (0x600 + 112) /* Select A register */ +#define PIOB_BSR (0x600 + 116) /* Select B register */ +#define PIOB_ABSR (0x600 + 120) /* AB Select status register */ +#define PIOB_OWER (0x600 + 160) /* Output Write enable register */ +#define PIOB_OWDR (0x600 + 164) /* Output write disable register */ +#define PIOB_OWSR (0x600 + 168) /* Output write status register */ +#define PIOC_PER (0x800) /* PIO Enable Register */ +#define PIOC_PDR (0x800 + 4) /* PIO Disable Register */ +#define PIOC_PSR (0x800 + 8) /* PIO status register */ +#define PIOC_OER (0x800 + 12) /* Output enable register */ +#define PIOC_ODR (0x800 + 20) /* Output disable register */ +#define PIOC_OSR (0x800 + 24) /* Output status register */ +#define PIOC_IFER (0x800 + 28) /* Input filter enable register */ +#define PIOC_IFDR (0x800 + 36) /* Input filter disable register */ +#define PIOC_IFSR (0x800 + 40) /* Input filter status register */ +#define PIOC_SODR (0x800 + 48) /* Set output data register */ +#define PIOC_CODR (0x800 + 52) /* Clear output data register */ +#define PIOC_ODSR (0x800 + 56) /* Output data status register */ +#define PIOC_PDSR (0x800 + 60) /* Pin data status register */ +#define PIOC_IER (0x800 + 64) /* Interrupt enable register */ +#define PIOC_IDR (0x800 + 68) /* Interrupt disable register */ +#define PIOC_IMR (0x800 + 72) /* Interrupt mask register */ +#define PIOC_ISR (0x800 + 76) /* Interrupt status register */ +#define PIOC_MDER (0x800 + 80) /* Multi driver enable register */ +#define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */ +#define PIOC_MDSR (0x800 + 88) /* Multi driver status register */ +#define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */ +#define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */ +#define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */ +#define PIOC_ASR (0x800 + 112) /* Select A register */ +#define PIOC_BSR (0x800 + 116) /* Select B register */ +#define PIOC_ABSR (0x800 + 120) /* AB Select status register */ +#define PIOC_OWER (0x800 + 160) /* Output Write enable register */ +#define PIOC_OWDR (0x800 + 164) /* Output write disable register */ +#define PIOC_OWSR (0x800 + 168) /* Output write status register */ +#define PIOD_PER (0xa00) /* PIO Enable Register */ +#define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */ +#define PIOD_PSR (0xa00 + 8) /* PIO status register */ +#define PIOD_OER (0xa00 + 12) /* Output enable register */ +#define PIOD_ODR (0xa00 + 20) /* Output disable register */ +#define PIOD_OSR (0xa00 + 24) /* Output status register */ +#define PIOD_IFER (0xa00 + 28) /* Input filter enable register */ +#define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */ +#define PIOD_IFSR (0xa00 + 40) /* Input filter status register */ +#define PIOD_SODR (0xa00 + 48) /* Set output data register */ +#define PIOD_CODR (0xa00 + 52) /* Clear output data register */ +#define PIOD_ODSR (0xa00 + 56) /* Output data status register */ +#define PIOD_PDSR (0xa00 + 60) /* Pin data status register */ +#define PIOD_IER (0xa00 + 64) /* Interrupt enable register */ +#define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */ +#define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */ +#define PIOD_ISR (0xa00 + 76) /* Interrupt status register */ +#define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */ +#define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */ +#define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */ +#define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */ +#define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */ +#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */ +#define PIOD_ASR (0xa00 + 112) /* Select A register */ +#define PIOD_BSR (0xa00 + 116) /* Select B register */ +#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */ +#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */ +#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ +#define PIOD_OWSR (0xa00 + 168) /* Output write status register */ /* IRQs : */ /* ==== //depot/projects/arm/src/sys/arm/at91/at91rm92timer.c#2 (text+ko) ==== @@ -53,7 +53,7 @@ static struct timecounter at91rm92timer_timecounter = { at91rm92timer_get_timecount, /* get_timecount */ NULL, /* no poll_pps */ - 0xffffu, /* counter_mask */ + 0xfffffu, /* counter_mask */ 32768, /* frequency */ "AT91RM9200 timer", /* name */ 0 /* quality */ @@ -72,6 +72,7 @@ timer_softc = device_get_softc(dev); timer_softc->sc_st = sc->sc_st; + timer_softc->dev = dev; if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_TIMER_BASE, AT91RM92_TIMER_SIZE, &timer_softc->sc_sh) != 0) panic("couldn't subregion timer registers"); @@ -97,19 +98,87 @@ static unsigned at91rm92timer_get_timecount(struct timecounter *tc) { - return (bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, - TIMER_PIMR)); + int cur1, cur2; + do { + cur1 = bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_CRTR); + cur2 = bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_CRTR); + } while (cur1 != cur2); + return (cur1); +} + +static void +clock_intr(void *frame) +{ + /* The interrupt is shared, so we have to make sure it's for us. */ + if (bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_SR) & 1) { + hardclock(frame); + } } void cpu_initclocks(void) { + int rel_value; + struct resource *irq; + int rid = 0; + void *ih; + device_t dev = timer_softc->dev; + + if (32768 % hz) { + printf("Cannot get %d Hz clock; using 128Hz\n", hz); + hz = 128; + } + rel_value = 32768 / hz; + /* Disable all interrupts. */ + bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_IDR, 0xffffffff); + /* The system timer shares the system irq (1) */ + irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1, 1, 1, RF_ACTIVE); + if (!irq) + panic("Unable to all irq for the system timer"); + else + bus_setup_intr(dev, irq, INTR_TYPE_CLK | INTR_FAST, + clock_intr, NULL, &ih); + + bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_PIMR, rel_value); + /* Real time counter increments every clock cycle. */ + bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_RTMR, 1); + + /* Enable PITS interrupts. */ + bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_IER, 1); tc_init(&at91rm92timer_timecounter); } void DELAY(int n) { + uint32_t usec = 0; + uint32_t cur1, cur2, old, delta = 0; + + old = bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, + TIMER_CRTR); + while (usec < n) { + do { + cur1 = bus_space_read_4(timer_softc->sc_st, + timer_softc->sc_sh, TIMER_CRTR); + cur2 = bus_space_read_4(timer_softc->sc_st, + timer_softc->sc_sh, TIMER_CRTR); + } while (cur1 != cur2); + if (old > cur1) + delta += (old + (0xfffff + 1 - cur1)); + else + delta += (cur1 - old); + usec += delta / 32768 * 1000000; + delta = 0; + + + } } void ==== //depot/projects/arm/src/sys/arm/at91/files.at91rm92#2 (text+ko) ==== @@ -3,3 +3,6 @@ arm/arm/irq_dispatch.S standard arm/at91/at91rm92.c standard arm/at91/at91rm92timer.c standard +arm/at91/uart_bus_at91rm92usart.c optional uart +arm/at91/uart_cpu_at91rm92usart.c optional uart +arm/at91/uart_dev_at91rm92usart.c optional uart ==== //depot/projects/arm/src/sys/arm/at91/files.kb920x#2 (text+ko) ==== ==== //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c#2 (text+ko) ==== @@ -95,9 +95,10 @@ #include <arm/at91/at91rm92reg.h> #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ -#define KERNEL_PT_BEFOREKERN 1 -#define KERNEL_PT_AFKERNEL 2 /* L2 table for mapping after kernel */ -#define KERNEL_PT_AFKERNEL_NUM 9 +#define KERNEL_PT_KERN 1 +#define KERNEL_PT_KERN_NUM 4 +#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */ +#define KERNEL_PT_AFKERNEL_NUM 5 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) @@ -137,7 +138,6 @@ struct pv_addr kernelstack; struct pv_addr minidataclean; -void enable_mmu(vm_offset_t); static struct trapframe proc0_tf; /* Static device mappings. */ @@ -188,6 +188,7 @@ i = 0; set_cpufuncs(); + cninit(); fake_preload[i++] = MODINFO_NAME; fake_preload[i++] = strlen("elf kernel") + 1; strcpy((char*)&fake_preload[i++], "elf kernel"); @@ -201,7 +202,7 @@ fake_preload[i++] = KERNBASE; fake_preload[i++] = MODINFO_SIZE; fake_preload[i++] = sizeof(uint32_t); - fake_preload[i++] = (uint32_t)&end - KERNBASE - 0x00200000; + fake_preload[i++] = (uint32_t)&end - KERNBASE; fake_preload[i++] = 0; fake_preload[i] = 0; preload_metadata = (void *)fake_preload; @@ -215,7 +216,7 @@ /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_pa, (np)); \ - (var).pv_va = (var).pv_pa + 0xa0000000; + (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); #define alloc_pages(var, np) \ (var) = freemempos; \ @@ -260,11 +261,12 @@ l1pagetable = kernel_l1pt.pv_va; /* Map the L2 pages tables in the L1 page table */ - pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), + pmap_link_l2pt(l1pagetable, ARM_VECTORS_LOW, &kernel_pt_table[KERNEL_PT_SYS]); - pmap_link_l2pt(l1pagetable, KERNBASE, - &kernel_pt_table[KERNEL_PT_BEFOREKERN]); - pmap_map_chunk(l1pagetable, KERNBASE, 0x20000000, + for (i = 0; i < KERNEL_PT_KERN_NUM; i++) + pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x100000, + &kernel_pt_table[KERNEL_PT_KERN + i]); + pmap_map_chunk(l1pagetable, KERNBASE, KERNPHYSADDR, (((uint32_t)(&end) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1), VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); afterkern = round_page(((vm_offset_t)&end + L1_S_SIZE) & ~(L1_S_SIZE @@ -292,7 +294,10 @@ pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); + pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa, + MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, @@ -314,6 +319,7 @@ */ + cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); set_stackptr(PSR_ABT32_MODE, @@ -334,7 +340,6 @@ * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); - cninit(); /* Set stack for exception handlers */ @@ -351,28 +356,33 @@ thread0.td_frame = &proc0_tf; pcpup->pc_curpcb = thread0.td_pcb; - /* Enable MMU, I-cache, D-cache, write buffer. */ - - arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); + arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL); - pmap_bootstrap(pmap_curmaxkvaddr, - 0xd0000000, &kernel_l1pt); + pmap_curmaxkvaddr = freemempos - KERNPHYSADDR + KERNVIRTADDR; + pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1); + pmap_bootstrap(freemempos - KERNPHYSADDR + KERNVIRTADDR, + KERNVIRTADDR + 3 * memsize, + &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, MSGBUF_SIZE); mutex_init(); i = 0; - dump_avail[0] = freemempos; - dump_avail[1] = 0x20000000 + memsize; + dump_avail[0] = KERNPHYSADDR; + dump_avail[1] = KERNPHYSADDR + memsize; dump_avail[2] = 0; dump_avail[3] = 0; + phys_avail[0] = freemempos; + phys_avail[1] = KERNPHYSADDR + memsize; + phys_avail[2] = 0; + phys_avail[3] = 0; /* Do basic tuning, hz etc */ init_param1(); init_param2(memsize / PAGE_SIZE); - avail_end = 0x20000000 + memsize - 1; + avail_end = KERNPHYSADDR + memsize - 1; kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); ==== //depot/projects/arm/src/sys/arm/conf/KB920X#2 (text+ko) ====
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