From owner-freebsd-mips@freebsd.org Tue Feb 2 16:01:00 2016 Return-Path: Delivered-To: freebsd-mips@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E0ABCA97E0B for ; Tue, 2 Feb 2016 16:00:59 +0000 (UTC) (envelope-from daemon-user@freebsd.org) Received: from phabric-backend.rbsd.freebsd.org (unknown [IPv6:2607:fc50:2000:101::1bb:73]) by mx1.freebsd.org (Postfix) with ESMTP id CD493C80 for ; Tue, 2 Feb 2016 16:00:59 +0000 (UTC) (envelope-from daemon-user@freebsd.org) Received: by phabric-backend.rbsd.freebsd.org (Postfix, from userid 1346) id CC67FFCBB; Tue, 2 Feb 2016 16:00:59 +0000 (UTC) Date: Tue, 2 Feb 2016 16:00:59 +0000 To: freebsd-mips@freebsd.org From: "adrian (Adrian Chadd)" Reply-to: D5078+328+dc979054174fbf17@reviews.freebsd.org Subject: [Differential] [Closed] D5078: Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for clearing hazards Message-ID: <443a3a5d6200dd47d8fc177ed908b79f@localhost.localdomain> X-Priority: 3 X-Phabricator-Sent-This-Message: Yes X-Mail-Transport-Agent: MetaMTA X-Auto-Response-Suppress: All X-Phabricator-Mail-Tags: , Thread-Topic: D5078: Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for clearing hazards X-Herald-Rules: <28> X-Phabricator-Projects: <#mips> X-Phabricator-To: X-Phabricator-To: X-Phabricator-To: X-Phabricator-To: X-Phabricator-Cc: Precedence: bulk In-Reply-To: References: Thread-Index: ZWFhM2QzMjgxMjA4NmFjYmE0OWZjZDU3NjY3IFaw0rs= MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="b1_443a3a5d6200dd47d8fc177ed908b79f" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.20 List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Feb 2016 16:01:00 -0000 --b1_443a3a5d6200dd47d8fc177ed908b79f Content-Type: text/plain; charset = "utf-8" Content-Transfer-Encoding: 8bit This revision was automatically updated to reflect the committed changes. Closed by commit rS295150: Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for (authored by adrian). CHANGED PRIOR TO COMMIT https://reviews.freebsd.org/D5078?vs=12746&id=12956#toc REPOSITORY rS FreeBSD src repository CHANGES SINCE LAST UPDATE https://reviews.freebsd.org/D5078?vs=12746&id=12956 REVISION DETAIL https://reviews.freebsd.org/D5078 AFFECTED FILES head/sys/mips/include/cpuregs.h CHANGE DETAILS diff --git a/head/sys/mips/include/cpuregs.h b/head/sys/mips/include/cpuregs.h --- a/head/sys/mips/include/cpuregs.h +++ b/head/sys/mips/include/cpuregs.h @@ -110,6 +110,7 @@ * C: Cacheable, coherency unspecified. * CNC: Cacheable non-coherent. * CC: Cacheable coherent. + * CCS: Cacheable coherent, shared read. * CCE: Cacheable coherent, exclusive read. * CCEW: Cacheable coherent, exclusive write. * CCUOW: Cacheable coherent, update on write. @@ -154,9 +155,20 @@ #define MIPS_CCA_CACHED 0x03 #endif -#if defined(CPU_MIPS1004K) -#define MIPS_CCA_UNCACHED 0x02 -#define MIPS_CCA_CACHED 0x05 +/* + * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support + * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent + * CCA 0x03 and Uncached Accelerated CCA 0x07 + */ +#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \ + defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV) +#define MIPS_CCA_CNC 0x03 +#define MIPS_CCA_CCE 0x04 +#define MIPS_CCA_CCS 0x05 +#define MIPS_CCA_UA 0x07 + +/* We use shared read CCA for CACHED CCA */ +#define MIPS_CCA_CACHED MIPS_CCA_CCS #endif #ifndef MIPS_CCA_UNCACHED @@ -214,8 +226,18 @@ #define COP0_SYNC .word 0xc0 /* ehb */ #elif defined(CPU_SB1) #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop -#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) -#define COP0_SYNC .word 0xc0 /* ehb */ +#elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \ + defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \ + defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \ + defined(CPU_PROAPTIV) +/* + * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00: + * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be + * removed, leaving only the EHB". + * Also, all MIPS32 Release 2 implementations have the EHB instruction, which + * resolves all execution hazards. The same goes for MIPS32 Release 3. + */ +#define COP0_SYNC .word 0xc0 /* ehb */ #else /* * Pick a reasonable default based on the "typical" spacing described in the EMAIL PREFERENCES https://reviews.freebsd.org/settings/panel/emailpreferences/ To: Sgalabov_gmail.com, MIPS, adrian, imp Cc: freebsd-mips-list --b1_443a3a5d6200dd47d8fc177ed908b79f Content-Type: text/x-patch; charset=utf-8; name="D5078.12956.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="D5078.12956.patch" ZGlmZiAtLWdpdCBhL2hlYWQvc3lzL21pcHMvaW5jbHVkZS9jcHVyZWdzLmggYi9oZWFkL3N5cy9t aXBzL2luY2x1ZGUvY3B1cmVncy5oCi0tLSBhL2hlYWQvc3lzL21pcHMvaW5jbHVkZS9jcHVyZWdz LmgKKysrIGIvaGVhZC9zeXMvbWlwcy9pbmNsdWRlL2NwdXJlZ3MuaApAQCAtMTEwLDYgKzExMCw3 IEBACiAgKglDOglDYWNoZWFibGUsIGNvaGVyZW5jeSB1bnNwZWNpZmllZC4KICAqCUNOQzoJQ2Fj aGVhYmxlIG5vbi1jb2hlcmVudC4KICAqCUNDOglDYWNoZWFibGUgY29oZXJlbnQuCisgKglDQ1M6 CUNhY2hlYWJsZSBjb2hlcmVudCwgc2hhcmVkIHJlYWQuCiAgKglDQ0U6CUNhY2hlYWJsZSBjb2hl cmVudCwgZXhjbHVzaXZlIHJlYWQuCiAgKglDQ0VXOglDYWNoZWFibGUgY29oZXJlbnQsIGV4Y2x1 c2l2ZSB3cml0ZS4KICAqCUNDVU9XOglDYWNoZWFibGUgY29oZXJlbnQsIHVwZGF0ZSBvbiB3cml0 ZS4KQEAgLTE1NCw5ICsxNTUsMjAgQEAKICNkZWZpbmUJTUlQU19DQ0FfQ0FDSEVECQkweDAzCiAj ZW5kaWYKIAotI2lmIGRlZmluZWQoQ1BVX01JUFMxMDA0SykKLSNkZWZpbmUJTUlQU19DQ0FfVU5D QUNIRUQJMHgwMgotI2RlZmluZQlNSVBTX0NDQV9DQUNIRUQJCTB4MDUKKy8qCisgKiAxMDA0SyBh bmQgMTA3NEsgY29yZXMsIGFzIHdlbGwgYXMgaW50ZXJBcHRpdiBhbmQgcHJvQXB0aXYgY29yZXMs IHN1cHBvcnQKKyAqIENhY2hlYWJsZSBDb2hlcmVudCBDQ0FzIDB4MDQgYW5kIDB4MDUsIGFzIHdl bGwgYXMgQ2FjaGVhYmxlIG5vbi1Db2hlcmVudAorICogQ0NBIDB4MDMgYW5kIFVuY2FjaGVkIEFj Y2VsZXJhdGVkIENDQSAweDA3CisgKi8KKyNpZiBkZWZpbmVkKENQVV9NSVBTMTAwNEspIHx8IGRl ZmluZWQoQ1BVX01JUFMxMDc0SykgfHwJXAorICAgIGRlZmluZWQoQ1BVX0lOVEVSQVBUSVYpIHx8 IGRlZmluZWQoQ1BVX1BST0FQVElWKQorI2RlZmluZQlNSVBTX0NDQV9DTkMJCTB4MDMKKyNkZWZp bmUJTUlQU19DQ0FfQ0NFCQkweDA0CisjZGVmaW5lCU1JUFNfQ0NBX0NDUwkJMHgwNQorI2RlZmlu ZQlNSVBTX0NDQV9VQQkJMHgwNworCisvKiBXZSB1c2Ugc2hhcmVkIHJlYWQgQ0NBIGZvciBDQUNI RUQgQ0NBICovCisjZGVmaW5lCU1JUFNfQ0NBX0NBQ0hFRAkJTUlQU19DQ0FfQ0NTCiAjZW5kaWYK IAogI2lmbmRlZglNSVBTX0NDQV9VTkNBQ0hFRApAQCAtMjE0LDggKzIyNiwxOCBAQAogI2RlZmlu ZQlDT1AwX1NZTkMJLndvcmQgMHhjMAkvKiBlaGIgKi8KICNlbGlmIGRlZmluZWQoQ1BVX1NCMSkK ICNkZWZpbmUgQ09QMF9TWU5DICBzc25vcDsgc3Nub3A7IHNzbm9wOyBzc25vcDsgc3Nub3A7IHNz bm9wOyBzc25vcDsgc3Nub3A7IHNzbm9wCi0jZWxpZiBkZWZpbmVkKENQVV9NSVBTNzRLKSB8fCBk ZWZpbmVkKENQVV9NSVBTMTAwNEspCi0jZGVmaW5lCUNPUDBfU1lOQwkgLndvcmQgMHhjMAkvKiBl aGIgKi8KKyNlbGlmIGRlZmluZWQoQ1BVX01JUFMyNEspIHx8IGRlZmluZWQoQ1BVX01JUFMzNEsp IHx8CQlcCisgICAgICBkZWZpbmVkKENQVV9NSVBTNzRLKSB8fCBkZWZpbmVkKENQVV9NSVBTMTAw NEspICB8fAlcCisgICAgICBkZWZpbmVkKENQVV9NSVBTMTA3NEspIHx8IGRlZmluZWQoQ1BVX0lO VEVSQVBUSVYpIHx8CVwKKyAgICAgIGRlZmluZWQoQ1BVX1BST0FQVElWKQorLyoKKyAqIEFjY29y ZGluZyB0byBNSVBTMzJ0bSBBcmNoaXRlY3R1cmUgZm9yIFByb2dyYW1tZXJzLCBWb2wuSUksIHJl di4gMi4wMDoKKyAqICJBcyBFSEIgYmVjb21lcyBzdGFuZGFyZCBpbiBNSVBTIGltcGxlbWVudGF0 aW9ucywgdGhlIHByZXZpb3VzIFNTTk9QcyBjYW4gYmUKKyAqICByZW1vdmVkLCBsZWF2aW5nIG9u bHkgdGhlIEVIQiIuCisgKiBBbHNvLCBhbGwgTUlQUzMyIFJlbGVhc2UgMiBpbXBsZW1lbnRhdGlv bnMgaGF2ZSB0aGUgRUhCIGluc3RydWN0aW9uLCB3aGljaAorICogcmVzb2x2ZXMgYWxsIGV4ZWN1 dGlvbiBoYXphcmRzLiBUaGUgc2FtZSBnb2VzIGZvciBNSVBTMzIgUmVsZWFzZSAzLgorICovCisj ZGVmaW5lCUNPUDBfU1lOQwkud29yZCAweGMwCS8qIGVoYiAqLwogI2Vsc2UKIC8qCiAgKiBQaWNr IGEgcmVhc29uYWJsZSBkZWZhdWx0IGJhc2VkIG9uIHRoZSAidHlwaWNhbCIgc3BhY2luZyBkZXNj cmliZWQgaW4gdGhlCgo= --b1_443a3a5d6200dd47d8fc177ed908b79f--