From owner-svn-src-head@freebsd.org Wed Aug 22 22:56:03 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5FB601098B5A; Wed, 22 Aug 2018 22:56:03 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 1672B71D7C; Wed, 22 Aug 2018 22:56:03 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D1B441988F; Wed, 22 Aug 2018 22:56:02 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w7MMu2g9070073; Wed, 22 Aug 2018 22:56:02 GMT (envelope-from gonzo@FreeBSD.org) Received: (from gonzo@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w7MMu2Hl070070; Wed, 22 Aug 2018 22:56:02 GMT (envelope-from gonzo@FreeBSD.org) Message-Id: <201808222256.w7MMu2Hl070070@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: gonzo set sender to gonzo@FreeBSD.org using -f From: Oleksandr Tymoshenko Date: Wed, 22 Aug 2018 22:56:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r338215 - head/sys/dev/ichiic X-SVN-Group: head X-SVN-Commit-Author: gonzo X-SVN-Commit-Paths: head/sys/dev/ichiic X-SVN-Commit-Revision: 338215 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Aug 2018 22:56:03 -0000 Author: gonzo Date: Wed Aug 22 22:56:01 2018 New Revision: 338215 URL: https://svnweb.freebsd.org/changeset/base/338215 Log: [ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16720 Modified: head/sys/dev/ichiic/ig4_acpi.c head/sys/dev/ichiic/ig4_iic.c head/sys/dev/ichiic/ig4_var.h Modified: head/sys/dev/ichiic/ig4_acpi.c ============================================================================== --- head/sys/dev/ichiic/ig4_acpi.c Wed Aug 22 22:19:42 2018 (r338214) +++ head/sys/dev/ichiic/ig4_acpi.c Wed Aug 22 22:56:01 2018 (r338215) @@ -68,10 +68,20 @@ static char *ig4iic_ids[] = { static int ig4iic_acpi_probe(device_t dev) { + ig4iic_softc_t *sc; + char *hid; - if (acpi_disabled("ig4iic") || - ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids) == NULL) - return (ENXIO); + sc = device_get_softc(dev); + + if (acpi_disabled("ig4iic")) + return (ENXIO); + + hid = ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids); + if (hid == NULL) + return (ENXIO); + + if (strcmp("AMDI0010", hid) == 0) + sc->access_intr_mask = 1; device_set_desc(dev, "Designware I2C Controller"); return (0); Modified: head/sys/dev/ichiic/ig4_iic.c ============================================================================== --- head/sys/dev/ichiic/ig4_iic.c Wed Aug 22 22:19:42 2018 (r338214) +++ head/sys/dev/ichiic/ig4_iic.c Wed Aug 22 22:56:01 2018 (r338215) @@ -724,6 +724,19 @@ ig4iic_intr(void *cookie) ++sc->rnext; status = reg_read(sc, IG4_REG_I2C_STA); } + + /* + * Workaround to trigger pending interrupt if IG4_REG_INTR_STAT + * is changed after clearing it + */ + if(sc->access_intr_mask) { + status = reg_read(sc, IG4_REG_INTR_MASK); + if(status) { + reg_write(sc, IG4_REG_INTR_MASK, 0); + reg_write(sc, IG4_REG_INTR_MASK, status); + } + } + wakeup(sc); mtx_unlock(&sc->io_lock); } Modified: head/sys/dev/ichiic/ig4_var.h ============================================================================== --- head/sys/dev/ichiic/ig4_var.h Wed Aug 22 22:19:42 2018 (r338214) +++ head/sys/dev/ichiic/ig4_var.h Wed Aug 22 22:56:01 2018 (r338215) @@ -72,6 +72,7 @@ struct ig4iic_softc { int slave_valid : 1; int read_started : 1; int write_started : 1; + int access_intr_mask : 1; /* * Locking semantics: