From owner-freebsd-current@FreeBSD.ORG Fri Aug 6 03:46:02 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 4B1E016A4CE; Fri, 6 Aug 2004 03:46:02 +0000 (GMT) Received: from pooker.samsco.org (pooker.samsco.org [168.103.85.57]) by mx1.FreeBSD.org (Postfix) with ESMTP id EA64A43D2D; Fri, 6 Aug 2004 03:46:01 +0000 (GMT) (envelope-from scottl@samsco.org) Received: from [192.168.0.201] ([192.168.0.201]) (authenticated bits=0) by pooker.samsco.org (8.12.11/8.12.10) with ESMTP id i763jEgQ009139; Thu, 5 Aug 2004 21:45:14 -0600 (MDT) (envelope-from scottl@samsco.org) Message-ID: <4112FE79.4020007@samsco.org> Date: Thu, 05 Aug 2004 21:43:53 -0600 From: Scott Long User-Agent: Mozilla/5.0 (X11; U; FreeBSD i386; en-US; rv:1.7.1) Gecko/20040801 X-Accept-Language: en-us, en MIME-Version: 1.0 To: John Baldwin References: <20040805050422.GA41201@cat.robbins.dropbear.id.au> <200408051759.53079.jhb@FreeBSD.org> In-Reply-To: <200408051759.53079.jhb@FreeBSD.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, hits=0.0 required=3.8 tests=none autolearn=no version=2.63 X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on pooker.samsco.org cc: freebsd-current@freebsd.org cc: Tim Robbins Subject: Re: Atomic operations on i386/amd64 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Aug 2004 03:46:02 -0000 John Baldwin wrote: > On Thursday 05 August 2004 01:04 am, Tim Robbins wrote: > >>Is there any particular reason why atomic_load_acq_*() and >>atomic_store_rel_*() are implemented with CMPXCHG and XCHG instead of >>MOV on i386/amd64 UP? > > > Actually, using mov instead of lock xchg for store_rel reduced performance in > some benchmarks Scott ran on an SMP machine, I'm guessing due to the higher > latency of locks becoming available to other CPUs. I'm still waiting for > benchmark results on UP to see if the change should be made under #ifndef SMP > or some such. > Your patch appears to slightly pessimize UP as well and SMP. Scott