Date: Fri, 18 Aug 1995 14:18:38 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: pete@sms.fi (Petri Helenius) Cc: freebsd-hardware@freebsd.org Subject: Re: i82424ZX vs i82424TX cache dram controller Message-ID: <199508182118.OAA27717@gndrsh.aac.dev.com> In-Reply-To: <199508181503.SAA29469@silver.sms.fi> from "Petri Helenius" at Aug 18, 95 06:03:25 pm
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> > Rodney W. Grimes writes: > > > > > > > still no rev message--from looking at source that seems to be in > > > -current and 2.0.5R but not in 2.0R > > > > Oopss.. your running old code :-(... > > What one should enable to get the verbose probe in 2.2-CURRENT? I get only: boot with the -v flag. > chip0 <Intel 82437 (Triton)> rev 1 on pci0:0 > chip1 <Intel 82371 (Triton)> rev 2 on pci0:7 > > ...and I'm wondering whether there is any parity checking on the chipset. Intel Triton does NOT have parity checking logic in the memory controller circuits. There is not parity checking in the chip set. > (I've been told that it's unlikely) You've now been told it does not, plain and simple. [I would have done this a long time ago, but NDA's are nasty things, Intel made this public information 3 weeks ago with the release of the Triton data sheets to the public, then formally stated it just recently (week or so) in a press release. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
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