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From: "Justin T. Gibbs" <gibbs@FreeBSD.org>
Date: Fri, 27 Jun 2003 21:42:11 -0700 (PDT)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org,
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X-FreeBSD-CVS-Branch: HEAD
Subject: cvs commit: src/sys/dev/aic7xxx aic79xx.c
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gibbs       2003/06/27 21:42:11 PDT

  FreeBSD src repository

  Modified files:
    sys/dev/aic7xxx      aic79xx.c 
  Log:
  Correct a typo in a comment.
  
  Add a comment in ahd_clear_critical_sections() about
  our need to leave ENBUSFREE set in SIMODE1 while single
  stepping.
  
  Re-arrange some delay loops so that we always perform
  a read after any register write and before the delay.
  This should make the delay loop more accurate.
  
  When completing message processing for a packetized
  commention, return the controller to a state where
  invalid non-packetized phases will still cause protocol
  violations.  These are the same operations as those
  performed in the clear_target_state routine in the
  firmware.
  
  Now that we have a chip with working ABORTPENDING
  support (the 7901B), comment out the automatic use
  of this feature until we can adequately test it.
  The previous checkin updated the bug mask for the
  7901B so this code was exercised.
  
  When resetting the bus, perform an ahd_flush_device_writes()
  call so that our reset assertion delay is acurately
  timed from when the reset bit is written to the controller.
  
  Revision  Changes    Path
  1.22      +23 -10    src/sys/dev/aic7xxx/aic79xx.c