Date: Fri, 1 Feb 2008 05:22:29 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 134582 for review Message-ID: <200802010522.m115MTPY068477@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=134582 Change 134582 by imp@imp_lighthouse on 2008/02/01 05:22:25 Add some ifdefs for TARGET_OCTEON preservinbg more bits. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#21 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/pm_machdep.c#6 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#12 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#21 (text+ko) ==== ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/pm_machdep.c#6 (text+ko) ==== @@ -484,6 +484,10 @@ #else td->td_frame->sr = SR_KSU_USER | SR_EXL;// mips2 also did COP_0_BIT #endif +#ifdef TARGET_OCTEON + td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | + MIPS_SR_KX | MIPS_SR_SX; +#endif /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#12 (text+ko) ==== @@ -169,6 +169,9 @@ td2->td_md.md_saved_intr = 1; td2->td_md.md_spinlock_count = 1; +#ifdef TARGET_OCTEON + pcb2->pcb_context.val[11] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; +#endif } @@ -304,6 +307,10 @@ /* Dont set IE bit in SR. sched lock release will take care of it */ /* idle_mask is jmips pcb2->pcb_context.val[11] = (ALL_INT_MASK & idle_mask); */ pcb2->pcb_context.val[11] = 0; +#ifdef TARGET_OCTEON + pcb2->pcb_context.val[11] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | + MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; +#endif /* * FREEBSD_DEVELOPERS_FIXME: @@ -314,6 +321,12 @@ /* SMP Setup to release sched_lock in fork_exit(). */ td->td_md.md_spinlock_count = 1; td->td_md.md_saved_intr = 1; +#if 0 + /* Maybe we need to fix this? */ + td->td_md.md_saved_sr = ( (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT) | + (MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX) | + (MIPS_SR_INT_IE | MIPS_HARD_INT_MASK)); +#endif } /* @@ -347,6 +360,10 @@ tf->a0 = (register_t)arg; tf->sr = SR_KSU_USER | SR_EXL; +#ifdef TARGET_OCTEON + tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_UX | + MIPS_SR_KX; +#endif /* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */ /**XXX the above may now be wrong -- mips2 implements this as panic */ /*
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