Date: Mon, 28 Apr 2003 15:46:24 -0700 (PDT) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 29982 for review Message-ID: <200304282246.h3SMkOtm060211@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=29982 Change 29982 by jmallett@jmallett_dalek on 2003/04/28 15:46:15 Add mips_idle and mips_wait_idle as variants of mips_maybewait_idle. Some of the code is ifXXX and really needs written to work with FreeBSD. Affected files ... .. //depot/projects/mips/sys/mips/mips/locore_mips3.S#3 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/locore_mips3.S#3 (text+ko) ==== @@ -94,6 +94,8 @@ #include <machine/param.h> #include <machine/endian.h> +#include "assym.s" + /* * XXX We need a cleaner way of handling the instruction hazards of * the various processors. Here are the relevant rules for the QED 52XX: @@ -354,3 +356,94 @@ * saved in trap frames and restores. */ LEAF(mips_cp0_status_write) + +LEAF(mips_wait_idle) + j mips_maybewait_idle + li t1, 1 +END(mips_wait_idle) + +LEAF(mips_idle) + j mips_maybewait_idle + move t1, zero +END(mips_idle) + +/* + * mips_maybewait_idle: + * + * When no processes are on the runq, cpu_switch branches to + * idle to wait for something to come ready. + * + * NOTE: This is really part of cpu_switch(), but defined here + * for kernel profiling. + * + * This version takes advantage of power-saving features on + * the QED RM52xx family of CPUs, and MIPS32 & MIPS64 CPUs, + * if t1 is non-zero. + */ +LEAF(mips_maybewait_idle) + la t0, pcpup + sd zero, PC_CURTHREAD(t0) # set curthread NULL +#if defined(LOCKDEBUG) + jal sched_unlock_idle # release sched_lock + nop +#endif + li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE) + DYNAMIC_STATUS_MASK(t0,t1) # machine dependent masking + mtc0 t0, MIPS_COP_0_STATUS # enable all interrupts + COP0_SYNC + nop + +#if XXX + /* Try to zero some free pages. */ + lw t0, uvm + UVM_PAGE_IDLE_ZERO + nop + beq t0, zero, 1f + nop + jal uvm_pageidlezero + nop +#endif +1: +#ifdef MIPS_DYNAMIC_STATUS_MASK + # Do this again since the mask may have changed. + li t3, (MIPS_INT_MASK | MIPS_SR_INT_IE) + DYNAMIC_STATUS_MASK(t3,t1) # machine dependent masking + mtc0 t3, MIPS_COP_0_STATUS # enable all interrupts + COP0_SYNC + nop +#endif +#if XXX + lw t0, sched_whichqs # look for non-empty queue + bne t0, zero, 1f + nop +#endif + beq t1, zero, 1b + nop + wait + nop + nop + nop + b 1b + nop +1: +#if defined(LOCKDEBUG) + mtc0 zero, MIPS_COP_0_STATUS # disable all interrupts + COP0_SYNC + nop + nop + nop + nop + jal _C_LABEL(sched_lock_idle) # acquire sched_lock + nop + la ra, cpu_switch_queuescan + j ra + nop +#else + mtc0 zero, MIPS_COP_0_STATUS # disable all interrupts + COP0_SYNC + nop + nop + nop + la ra, cpu_switch_queuescan + j ra + nop +END(mips_maybewait_idle)
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