Date: Wed, 17 Apr 2019 13:17:39 -0700 From: Mark Millard <marklmi@yahoo.com> To: FreeBSD PowerPC ML <freebsd-ppc@freebsd.org>, Justin Hibbits <chmeeedalf@gmail.com> Subject: powerpc64 and 32-bit FreeBSD, powerpc mttb(time) use vs. interrupts: should interrupts be disabled around the 3 mtspr's? Message-ID: <1202CA56-C1A7-441C-9854-F5790C8F9D7B@yahoo.com>
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For:
static __inline void
mttb(u_quad_t time)
{
mtspr(TBR_TBWL, 0);
mtspr(TBR_TBWU, (uint32_t)(time >> 32));
mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
}
an example use of the powerpc code is:
<powermac_smp_timebase_sync> li r3,0
<powermac_smp_timebase_sync+0x4> rldicl r5,r4,32,32
<powermac_smp_timebase_sync+0x8> mttbl r3
<powermac_smp_timebase_sync+0xc> mttbu r5
<powermac_smp_timebase_sync+0x10> mttbl r4
<powermac_smp_timebase_sync+0x14> blr
Nothing about this prevents interrupts between
powermac_smp_timebase_sync+0x8 and powermac_smp_timebase_sync+0xc
or between
powermac_smp_timebase_sync+0xc and powermac_smp_timebase_sync+0x8=10 .
The code sequence is not atomic for the time base
assignment.
Should mttb be something more like:
static __inline void
mttb(u_quad_t time)
{
const uint32_t high= time>>32;
const uint32_t low= time&0xffffffffu;
const register_t predisable_msr= intr_disable();
mtspr(TBR_TBWL, 0);
mtspr(TBR_TBWU, high);
mtspr(TBR_TBWL, low);
intr_restore(predisable_msr);
}
Or is the mttb usage guaranteed to only be in contexts
without any interrupts?
===
Mark Millard
marklmi at yahoo.com
( dsl-only.net went
away in early 2018-Mar)
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