Date: Fri, 20 Sep 2002 21:01:59 -0700 (PDT) From: Peter Wemm <peter@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 17825 for review Message-ID: <200209210401.g8L41xur015224@freefall.freebsd.org>
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http://people.freebsd.org/~peter/p4db/chv.cgi?CH=17825 Change 17825 by peter@peter_daintree on 2002/09/20 21:01:47 more decruftification. We dont have no nexgen or cyrix x86_64 cpus to deal with. Everything has cpuid. Affected files ... .. //depot/projects/hammer/sys/x86_64/include/md_var.h#5 edit .. //depot/projects/hammer/sys/x86_64/include/specialreg.h#2 edit .. //depot/projects/hammer/sys/x86_64/isa/isa.h#3 edit .. //depot/projects/hammer/sys/x86_64/isa/isa_dma.c#2 edit .. //depot/projects/hammer/sys/x86_64/isa/npx.c#9 edit .. //depot/projects/hammer/sys/x86_64/x86_64/locore.s#7 edit .. //depot/projects/hammer/sys/x86_64/x86_64/trap.c#9 edit Differences ... ==== //depot/projects/hammer/sys/x86_64/include/md_var.h#5 (text+ko) ==== @@ -44,7 +44,6 @@ extern u_int cpu_id; extern u_int cpu_fxsr; extern char cpu_vendor[]; -extern u_int cyrix_did; extern uint16_t *elan_mmcr; extern char kstack[]; extern char sigcode[]; ==== //depot/projects/hammer/sys/x86_64/include/specialreg.h#2 (text+ko) ==== @@ -168,69 +168,6 @@ #define MTRR_N16K 16 #define MTRR_N4K 64 -/* - * Cyrix configuration registers, accessible as IO ports. - */ -#define CCR0 0xc0 /* Configuration control register 0 */ -#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is - non-cacheable */ -#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ -#define CCR0_A20M 0x04 /* Enables A20M# input pin */ -#define CCR0_KEN 0x08 /* Enables KEN# input pin */ -#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ -#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold - state */ -#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set - assoc */ -#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* Configuration control register 1 */ -#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ -#define CCR1_SMI 0x02 /* Enables SMM pins */ -#define CCR1_SMAC 0x04 /* System management memory access */ -#define CCR1_MMAC 0x08 /* Main memory access */ -#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ -#define CCR1_SM3 0x80 /* SMM address space address region 3 */ - -#define CCR2 0xc2 -#define CCR2_WB 0x02 /* Enables WB cache interface pins */ -#define CCR2_SADS 0x02 /* Slow ADS */ -#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ -#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ -#define CCR2_WT1 0x10 /* WT region 1 */ -#define CCR2_WPR1 0x10 /* Write-protect region 1 */ -#define CCR2_BARB 0x20 /* Flushes write-back cache when entering - hold state. */ -#define CCR2_BWRT 0x40 /* Enables burst write cycles */ -#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ - -#define CCR3 0xc3 -#define CCR3_SMILOCK 0x01 /* SMM register lock */ -#define CCR3_NMI 0x02 /* Enables NMI during SMM */ -#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ -#define CCR3_SMMMODE 0x08 /* SMM Mode */ -#define CCR3_MAPEN0 0x10 /* Enables Map0 */ -#define CCR3_MAPEN1 0x20 /* Enables Map1 */ -#define CCR3_MAPEN2 0x40 /* Enables Map2 */ -#define CCR3_MAPEN3 0x80 /* Enables Map3 */ - -#define CCR4 0xe8 -#define CCR4_IOMASK 0x07 -#define CCR4_MEM 0x08 /* Enables momory bypassing */ -#define CCR4_DTE 0x10 /* Enables directory table entry cache */ -#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ -#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ - -#define CCR5 0xe9 -#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ -#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ -#define CCR5_LBR1 0x10 /* Local bus region 1 */ -#define CCR5_ARREN 0x20 /* Enables ARR region */ - -#define CCR6 0xea - -#define CCR7 0xeb - /* Performance Control Register (5x86 only). */ #define PCR0 0x20 #define PCR0_RSTK 0x01 /* Enables return stack */ @@ -339,21 +276,4 @@ #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ - -#ifndef LOCORE -static __inline u_char -read_cyrix_reg(u_char reg) -{ - outb(0x22, reg); - return inb(0x23); -} - -static __inline void -write_cyrix_reg(u_char reg, u_char data) -{ - outb(0x22, reg); - outb(0x23, data); -} -#endif - #endif /* !_MACHINE_SPECIALREG_H_ */ ==== //depot/projects/hammer/sys/x86_64/isa/isa.h#3 (text+ko) ==== @@ -165,32 +165,4 @@ #endif /* !IO_ISASIZES */ -/* - * Input / Output Memory Physical Addresses - */ -#ifndef IOM_BEGIN -#define IOM_BEGIN 0x0A0000 /* Start of I/O Memory "hole" */ -#define IOM_END 0x100000 /* End of I/O Memory "hole" */ -#define IOM_SIZE (IOM_END - IOM_BEGIN) -#endif /* !IOM_BEGIN */ - -/* - * RAM Physical Address Space (ignoring the above mentioned "hole") - */ -#ifndef RAM_BEGIN -#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ -#define RAM_END 0x1000000 /* End of RAM Memory */ -#define RAM_SIZE (RAM_END - RAM_BEGIN) -#endif /* !RAM_BEGIN */ - -/* - * Oddball Physical Memory Addresses - */ -#ifndef COMPAQ_RAMRELOC -#define COMPAQ_RAMRELOC 0x80C00000 /* Compaq RAM relocation/diag */ -#define COMPAQ_RAMSETUP 0x80C00002 /* Compaq RAM setup */ -#define WEITEK_FPU 0xC0000000 /* WTL 2167 */ -#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ -#endif /* !COMPAQ_RAMRELOC */ - #endif /* !_I386_ISA_ISA_H_ */ ==== //depot/projects/hammer/sys/x86_64/isa/isa_dma.c#2 (text+ko) ==== @@ -79,6 +79,8 @@ #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ +#define ISARAM_END 0x1000000 + static int isa_dmarangecheck(caddr_t va, u_int length, int chan); static caddr_t dma_bouncebuf[8]; @@ -381,7 +383,6 @@ endva = (vm_offset_t)round_page((vm_offset_t)va + length); for (; va < (caddr_t) endva ; va += PAGE_SIZE) { phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va)); -#define ISARAM_END RAM_END if (phys == 0) panic("isa_dmacheck: no physical page present"); if (phys >= ISARAM_END) ==== //depot/projects/hammer/sys/x86_64/isa/npx.c#9 (text+ko) ==== @@ -549,17 +549,13 @@ pcb->pcb_flags |= PCB_NPXINITDONE; } else { /* - * The following frstor may cause an IRQ13 when the state + * The following frstor may cause a trap when the state * being restored has a pending error. The error will * appear to have been triggered by the current (npx) user * instruction even when that instruction is a no-wait * instruction that should not trigger an error (e.g., * instructions are broken the same as frstor, so our - * treatment does not amplify the breakage. On at least - * one 386/Cyrix 387 system, fnclex works correctly while - * frstor and fnsave are broken, so our treatment breaks - * fnclex if it is the first FPU instruction after a context - * switch. + * treatment does not amplify the breakage. */ fpurstor(&pcb->pcb_save); } ==== //depot/projects/hammer/sys/x86_64/x86_64/locore.s#7 (text+ko) ==== @@ -491,93 +491,6 @@ */ identify_cpu: - /* Try to toggle alignment check flag; does not exist on 386. */ - pushfl - popl %eax - movl %eax,%ecx - orl $PSL_AC,%eax - pushl %eax - popfl - pushfl - popl %eax - xorl %ecx,%eax - andl $PSL_AC,%eax - pushl %ecx - popfl - - testl %eax,%eax - jnz try486 - - /* NexGen CPU does not have aligment check flag. */ - pushfl - movl $0x5555, %eax - xorl %edx, %edx - movl $2, %ecx - clc - divl %ecx - jz trynexgen - popfl - movl $CPU_386,R(cpu) - jmp 3f - -trynexgen: - popfl - movl $CPU_NX586,R(cpu) - movl $0x4778654e,R(cpu_vendor) # store vendor string - movl $0x72446e65,R(cpu_vendor+4) - movl $0x6e657669,R(cpu_vendor+8) - movl $0,R(cpu_vendor+12) - jmp 3f - -try486: /* Try to toggle identification flag; does not exist on early 486s. */ - pushfl - popl %eax - movl %eax,%ecx - xorl $PSL_ID,%eax - pushl %eax - popfl - pushfl - popl %eax - xorl %ecx,%eax - andl $PSL_ID,%eax - pushl %ecx - popfl - - testl %eax,%eax - jnz trycpuid - movl $CPU_486,R(cpu) - - /* - * Check Cyrix CPU - * Cyrix CPUs do not change the undefined flags following - * execution of the divide instruction which divides 5 by 2. - * - * Note: CPUID is enabled on M2, so it passes another way. - */ - pushfl - movl $0x5555, %eax - xorl %edx, %edx - movl $2, %ecx - clc - divl %ecx - jnc trycyrix - popfl - jmp 3f /* You may use Intel CPU. */ - -trycyrix: - popfl - /* - * IBM Bluelighting CPU also doesn't change the undefined flags. - * Because IBM doesn't disclose the information for Bluelighting - * CPU, we couldn't distinguish it from Cyrix's (including IBM - * brand of Cyrix CPUs). - */ - movl $0x69727943,R(cpu_vendor) # store vendor string - movl $0x736e4978,R(cpu_vendor+4) - movl $0x64616574,R(cpu_vendor+8) - jmp 3f - -trycpuid: /* Use the `cpuid' instruction. */ xorl %eax,%eax cpuid # cpuid 0 movl %eax,R(cpu_high) # highest capability @@ -590,24 +503,8 @@ cpuid # cpuid 1 movl %eax,R(cpu_id) # store cpu_id movl %edx,R(cpu_feature) # store cpu_feature - rorl $8,%eax # extract family type - andl $15,%eax - cmpl $5,%eax - jae 1f - /* less than Pentium; must be 486 */ - movl $CPU_486,R(cpu) - jmp 3f -1: - /* a Pentium? */ - cmpl $5,%eax - jne 2f - movl $CPU_586,R(cpu) - jmp 3f -2: - /* Greater than Pentium...call it a Pentium Pro */ - movl $CPU_686,R(cpu) -3: + movl $CPU_686,R(cpu) # call it a pentium pro ret ==== //depot/projects/hammer/sys/x86_64/x86_64/trap.c#9 (text+ko) ==== @@ -222,12 +222,6 @@ code = frame.tf_err; if (type == T_PAGEFLT) { /* - * For some Cyrix CPUs, %cr2 is clobbered by - * interrupts. This problem is worked around by using - * an interrupt gate for the pagefault handler. We - * are finally ready to read %cr2 and then must - * reenable interrupts. - * * If we get a page fault while holding a spin lock, then * it is most likely a fatal kernel page fault. The kernel * is already going to panic trying to get a sleep lock to @@ -236,9 +230,7 @@ * to the debugger. */ eva = rcr2(); - if (PCPU_GET(spinlocks) == NULL) - enable_intr(); - else + if (PCPU_GET(spinlocks) != NULL) trap_fatal(&frame, eva); } To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the message
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