Date: Sun, 30 Oct 2005 03:02:13 +0800 From: Dinesh Nair <dinesh@alphaque.com> To: Paul Hamilton <paulh@bdug.org.au> Cc: freebsd-questions@freebsd.org Subject: Re: Can FreeBSD 4.11 and 5.4 run on a HP DL-140 G2 server? Message-ID: <4363C735.4030203@alphaque.com> In-Reply-To: <024e01c5dc88$40f35900$6600a8c0@w2k2> References: <024e01c5dc88$40f35900$6600a8c0@w2k2>
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This is a multi-part message in MIME format. --------------090801000704050601040902 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 10/29/05 20:57 Paul Hamilton said the following: > Where did you get the patch from? i wrote it. find attached. :) these will add support to the intel ICH7 SATA controller as well as the ITE 8211F and ITE 8212F controllers. i've yet to test the SATA 150 RAID on the intel ICH7, hence the commented out device id in the driver. do let me know if this works when you've tested it. -- Regards, /\_/\ "All dogs go to heaven." dinesh@alphaque.com (0 0) http://www.alphaque.com/ +==========================----oOO--(_)--OOo----==========================+ | for a in past present future; do | | for b in clients employers associates relatives neighbours pets; do | | echo "The opinions here in no way reflect the opinions of my $a $b." | | done; done | +=========================================================================+ --------------090801000704050601040902 Content-Type: text/plain; name="ata-pci.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ata-pci.c.diff" --- ata-pci.c.orig Wed Oct 19 11:44:18 2005 +++ ata-pci.c Wed Oct 19 12:48:11 2005 @@ -186,6 +187,30 @@ pci_write_config(dev, 0xa4, pci_read_config(dev, 0xa4, 4), 4); return "Intel ICH6 SATA150 controller"; + + case 0x27c08086: /* Intel ICH7 SATA */ +#if 0 + case 0x27c38086: /* Intel ICH7 SATA RAID */ +#endif + /* Clear SATA error registers */ + pci_write_config(dev, 0xa0, 0x54, 4); + pci_write_config(dev, 0xa4, pci_read_config(dev, 0xa4, 4), 4); + pci_write_config(dev, 0xa0, 0x64, 4); + pci_write_config(dev, 0xa4, pci_read_config(dev, 0xa4, 4), 4); + + return "Intel ICH7 SATA controller"; + + case 0x82111283: /* ITE 8211F */ + case 0x82121283: /* ITE 8212F */ + /* set PCI mode and 66Mhz reference clock */ + pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); + + /* set default active & recover timings */ + pci_write_config(dev, 0x54, 0x31, 1); + /* set default UDMA timing */ + pci_write_config(dev, 0x56, 0x31, 1); + + return "ITE 8211F/8212F PCI Controller" ; case 0x522910b9: if (pci_get_revid(dev) >= 0xc4) @@ -669,6 +696,10 @@ case 0x25a38086: /* Intel 6300ESB SATA150 */ case 0x25b08086: /* Intel 6300ESB SATA150 RAID */ case 0x26518086: /* Intel ICH6 SATA150 */ + case 0x27c08086: /* Intel ICH7 SATA */ +#if 0 + case 0x27c38086: /* Intel ICH7 SATA RAID */ +#endif dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) --------------090801000704050601040902 Content-Type: text/plain; name="ata-dma.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ata-dma.c.diff" --- ata-dma.c.orig Wed Oct 19 02:14:39 2005 +++ ata-dma.c Sun Oct 30 02:56:31 2005 @@ -50,6 +50,7 @@ static void promise_timing(struct ata_device *, int, int); static void hpt_timing(struct ata_device *, int, int); static int hpt_cable80(struct ata_device *); +static int ata_mode2idx(int mode); /* misc defines */ #define ATAPI_DEVICE(atadev) \ @@ -187,6 +188,7 @@ int devno = (channel << 1) + device; int error; int32_t mask54 = 0; + int mode = udmamode ; /* set our most pessimistic default mode */ atadev->mode = ATA_PIO; @@ -200,6 +202,7 @@ case 0x25a38086: /* Intel 6300ESB SATA150 */ case 0x25b08086: /* Intel 6300ESB SATA150 RAID */ case 0x26518086: /* Intel ICH6 SATA150 */ + case 0x27c08086: /* Intel ICH7 SATA */ if (!panicstr) udmamode = 5; break; @@ -228,6 +231,60 @@ #endif switch (chiptype) { + case 0x82111283: /* ITE 8211F */ + case 0x82121283: /* ITE 8212F */ + + if(udmamode == 2) + mode = ATA_UDMA2; + else + mode = ATA_UDMA5; + + /* set the mode on the device */ + error = ata_command(atadev, ATA_C_SETFEATURES, 0, + mode, ATA_C_F_SETXFER,ATA_WAIT_READY); + + if(bootverbose) + ata_prtdev(atadev, "%s setting %s on ITE8212F chip\n", + (error) ? "failed" : "success", ata_mode2str(mode)); + + /* if the device accepted the mode change, setup HW accordingly */ + if(!error) { + if(mode >= ATA_UDMA) { + u_int8_t udmatiming[] = + { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; + + /* enable UDMA mode */ + pci_write_config(parent, 0x50, + pci_read_config(parent, 0x50, 1) & + ~(1 << (devno + 3)), 1); + /* set UDMA timing */ + pci_write_config(parent, + 0x56 + (channel << 2) + ATA_DEV(atadev->unit), + udmatiming[mode & ATA_MODE_MASK], 1); + + ata_dmacreate(atadev, apiomode, mode); + return ; + } + else { + u_int8_t chtiming[] = + { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; + + /* disable UDMA mode */ + pci_write_config(parent, 0x50, + pci_read_config(parent, 0x50, 1) | + (1 << (devno + 3)), 1); + + /* set active and recover timing (shared between master and slave */ + if(pci_read_config(parent, 0x54 + (channel << 2), 1) < + chtiming[ata_mode2idx(mode)]) + pci_write_config(parent, 0x54 + (channel << 2), + chtiming[ata_mode2idx(mode)], 1); + } + } + break ; + + + case 0x24db8086: /* Intel ICH5 */ case 0x24d18086: /* Intel ICH5 SATA150 */ case 0x24df8086: /* Intel ICH5 SATA150 RAID */ @@ -1691,4 +1748,14 @@ res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); pci_write_config(parent, reg, val, 1); return !res; +} + +static int +ata_mode2idx(int mode) +{ + if ((mode & ATA_DMA_MASK) == ATA_UDMA) + return (mode & ATA_MODE_MASK) + 8; + if ((mode & ATA_DMA_MASK) == ATA_WDMA) + return (mode & ATA_MODE_MASK) + 5; + return (mode & ATA_MODE_MASK) - ATA_PIO0; } --------------090801000704050601040902--
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