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Date:      Mon, 2 Dec 2013 03:36:44 +0000 (UTC)
From:      Eitan Adler <eadler@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r258822 - head/sys/dev/drm2/i915
Message-ID:  <201312020336.rB23aid9088951@svn.freebsd.org>

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Author: eadler
Date: Mon Dec  2 03:36:44 2013
New Revision: 258822
URL: http://svnweb.freebsd.org/changeset/base/258822

Log:
  Partial revert of r258779 and r258780:
  	The directory sys/dev/drm2/i915 is apperently contributed code.
  	Revert to the broken version of this file to make future imports easier.
  
  Requested by:	kib

Modified:
  head/sys/dev/drm2/i915/i915_reg.h

Modified: head/sys/dev/drm2/i915/i915_reg.h
==============================================================================
--- head/sys/dev/drm2/i915/i915_reg.h	Mon Dec  2 03:11:25 2013	(r258821)
+++ head/sys/dev/drm2/i915/i915_reg.h	Mon Dec  2 03:36:44 2013	(r258822)
@@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$");
 #define _DPLL_A	0x06014
 #define _DPLL_B	0x06018
 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
-#define   DPLL_VCO_ENABLE		(1U << 31)
+#define   DPLL_VCO_ENABLE		(1 << 31)
 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
 #define   DPLL_VGA_MODE_DIS		(1 << 28)
@@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$");
 /* SDVO port control */
 #define SDVOB			0x61140
 #define SDVOC			0x61160
-#define   SDVO_ENABLE		(1U << 31)
+#define   SDVO_ENABLE		(1 << 31)
 #define   SDVO_PIPE_B_SELECT	(1 << 30)
 #define   SDVO_STALL_SELECT	(1 << 29)
 #define   SDVO_INTERRUPT_ENABLE	(1 << 26)
@@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$");
 #define DVOA			0x61120
 #define DVOB			0x61140
 #define DVOC			0x61160
-#define   DVO_ENABLE			(1U << 31)
+#define   DVO_ENABLE			(1 << 31)
 #define   DVO_PIPE_B_SELECT		(1 << 30)
 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
 #define   DVO_PIPE_STALL		(1 << 28)
@@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$");
  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  * the DPLL semantics change when the LVDS is assigned to that pipe.
  */
-#define   LVDS_PORT_EN			(1U << 31)
+#define   LVDS_PORT_EN			(1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT		(1 << 30)
 #define   LVDS_PIPE_MASK		(1 << 30)
@@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$");
 /* Video Data Island Packet control */
 #define VIDEO_DIP_DATA		0x61178
 #define VIDEO_DIP_CTL		0x61170
-#define   VIDEO_DIP_ENABLE		(1U << 31)
+#define   VIDEO_DIP_ENABLE		(1 << 31)
 #define   VIDEO_DIP_PORT_B		(1 << 29)
 #define   VIDEO_DIP_PORT_C		(2 << 29)
 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
@@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$");
 
 /* Panel power sequencing */
 #define PP_STATUS	0x61200
-#define   PP_ON		(1U << 31)
+#define   PP_ON		(1 << 31)
 /*
  * Indicates that all dependencies of the panel are on:
  *
@@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$");
 
 /* Panel fitting */
 #define PFIT_CONTROL	0x61230
-#define   PFIT_ENABLE		(1U << 31)
+#define   PFIT_ENABLE		(1 << 31)
 #define   PFIT_PIPE_MASK	(3 << 29)
 #define   PFIT_PIPE_SHIFT	29
 #define   VERT_INTERP_DISABLE	(0 << 10)
@@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$");
 /* TV port control */
 #define TV_CTL			0x68000
 /** Enables the TV encoder */
-# define TV_ENC_ENABLE			(1U << 31)
+# define TV_ENC_ENABLE			(1 << 31)
 /** Sources the TV encoder input from pipe B instead of A. */
 # define TV_ENC_PIPEB_SELECT		(1 << 30)
 /** Outputs composite video (DAC A only) */
@@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$");
  *
  * This gets cleared when TV_DAC_STATE_EN is cleared
 */
-# define TVDAC_STATE_CHG		(1U << 31)
+# define TVDAC_STATE_CHG		(1 << 31)
 # define TVDAC_SENSE_MASK		(7 << 28)
 /** Reports that DAC A voltage is above the detect threshold */
 # define TVDAC_A_SENSE			(1 << 30)
@@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$");
 
 #define TV_H_CTL_2		0x68034
 /** Enables the colorburst (needed for non-component color) */
-# define TV_BURST_ENA			(1U << 31)
+# define TV_BURST_ENA			(1 << 31)
 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
 # define TV_HBURST_START_SHIFT		16
 # define TV_HBURST_START_MASK		0x1fff0000
@@ -1958,7 +1958,7 @@ __FBSDID("$FreeBSD$");
 
 #define TV_V_CTL_3		0x68044
 /** Enables generation of the equalization signal */
-# define TV_EQUAL_ENA			(1U << 31)
+# define TV_EQUAL_ENA			(1 << 31)
 /** Length of vsync, in half lines */
 # define TV_VEQ_LEN_MASK		0x007f0000
 # define TV_VEQ_LEN_SHIFT		16
@@ -2032,7 +2032,7 @@ __FBSDID("$FreeBSD$");
 
 #define TV_SC_CTL_1		0x68060
 /** Turns on the first subcarrier phase generation DDA */
-# define TV_SC_DDA1_EN			(1U << 31)
+# define TV_SC_DDA1_EN			(1 << 31)
 /** Turns on the first subcarrier phase generation DDA */
 # define TV_SC_DDA2_EN			(1 << 30)
 /** Turns on the first subcarrier phase generation DDA */
@@ -2095,7 +2095,7 @@ __FBSDID("$FreeBSD$");
  * If set, the rest of the registers are ignored, and the calculated values can
  * be read back from the register.
  */
-# define TV_AUTO_SCALE			(1U << 31)
+# define TV_AUTO_SCALE			(1 << 31)
 /**
  * Disables the vertical filter.
  *
@@ -2158,7 +2158,7 @@ __FBSDID("$FreeBSD$");
 # define TV_VSCALE_IP_FRAC_SHIFT		0
 
 #define TV_CC_CONTROL		0x68090
-# define TV_CC_ENABLE			(1U << 31)
+# define TV_CC_ENABLE			(1 << 31)
 /**
  * Specifies which field to send the CC data in.
  *
@@ -2174,7 +2174,7 @@ __FBSDID("$FreeBSD$");
 # define TV_CC_LINE_SHIFT		0
 
 #define TV_CC_DATA		0x68094
-# define TV_CC_RDY			(1U << 31)
+# define TV_CC_RDY			(1 << 31)
 /** Second word of CC data to be transmitted. */
 # define TV_CC_DATA_2_MASK		0x007f0000
 # define TV_CC_DATA_2_SHIFT		16
@@ -2197,7 +2197,7 @@ __FBSDID("$FreeBSD$");
 #define DP_C				0x64200
 #define DP_D				0x64300
 
-#define   DP_PORT_EN			(1U << 31)
+#define   DP_PORT_EN			(1 << 31)
 #define   DP_PIPEB_SELECT		(1 << 30)
 #define   DP_PIPE_MASK			(1 << 30)
 
@@ -2307,7 +2307,7 @@ __FBSDID("$FreeBSD$");
 #define DPD_AUX_CH_DATA4		0x64320
 #define DPD_AUX_CH_DATA5		0x64324
 
-#define   DP_AUX_CH_CTL_SEND_BUSY	    (1U << 31)
+#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
@@ -2903,7 +2903,7 @@ __FBSDID("$FreeBSD$");
 
 /* VBIOS regs */
 #define VGACNTRL		0x71400
-# define VGA_DISP_DISABLE			(1U << 31)
+# define VGA_DISP_DISABLE			(1 << 31)
 # define VGA_2X_MODE				(1 << 30)
 # define VGA_PIPE_B_SELECT			(1 << 29)
 
@@ -3029,7 +3029,7 @@ __FBSDID("$FreeBSD$");
 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
 
 /* interrupts */
-#define DE_MASTER_IRQ_CONTROL   (1U << 31)
+#define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
 #define DE_PLANEB_FLIP_DONE     (1 << 27)
@@ -3553,7 +3553,7 @@ __FBSDID("$FreeBSD$");
 
 /* or SDVOB */
 #define HDMIB   0xe1140
-#define  PORT_ENABLE    (1U << 31)
+#define  PORT_ENABLE    (1 << 31)
 #define  TRANSCODER(pipe)       ((pipe) << 30)
 #define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
 #define  TRANSCODER_MASK        (1 << 30)
@@ -3583,13 +3583,13 @@ __FBSDID("$FreeBSD$");
 #define  LVDS_DETECTED	(1 << 1)
 
 #define BLC_PWM_CPU_CTL2	0x48250
-#define  PWM_ENABLE		(1U << 31)
+#define  PWM_ENABLE		(1 << 31)
 #define  PWM_PIPE_A		(0 << 29)
 #define  PWM_PIPE_B		(1 << 29)
 #define BLC_PWM_CPU_CTL		0x48254
 
 #define BLC_PWM_PCH_CTL1	0xc8250
-#define  PWM_PCH_ENABLE		(1U << 31)
+#define  PWM_PCH_ENABLE		(1 << 31)
 #define  PWM_POLARITY_ACTIVE_LOW	(1 << 29)
 #define  PWM_POLARITY_ACTIVE_HIGH	(0 << 29)
 #define  PWM_POLARITY_ACTIVE_LOW2	(1 << 28)
@@ -3611,8 +3611,8 @@ __FBSDID("$FreeBSD$");
 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
 #define  EDP_PANEL		(1 << 30)
-#define  PANEL_PORT_SELECT_DPC	(2U << 30)
-#define  PANEL_PORT_SELECT_DPD	(3U << 30)
+#define  PANEL_PORT_SELECT_DPC	(2 << 30)
+#define  PANEL_PORT_SELECT_DPD	(3 << 30)
 #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
 #define  PANEL_POWER_UP_DELAY_SHIFT	16
 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)



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