Date: Sun, 20 Jun 2004 21:28:41 +0200 From: Alexander Leidinger <Alexander@Leidinger.net> To: John Polstra <jdp@polstra.com> Cc: Radek Kozlowski <radek@raadradd.com> Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? Message-ID: <20040620212841.70071aa4@Magellan.Leidinger.net> In-Reply-To: <XFMail.20040616093540.jdp@polstra.com> References: <40D07430.1070504@raadradd.com> <XFMail.20040616093540.jdp@polstra.com>
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On Wed, 16 Jun 2004 09:35:40 -0700 (PDT) John Polstra <jdp@polstra.com> wrote: [misc/cpuid] > Yes, but it gives working code that generally shows how to get the > information. Here's a link to an Intel document "Intel(R) Processor > Idientification and the CPUID Instruction" that covers the newer CPUs: > > http://www.intel.com/design/Xeon/applnots/24161825.pdf Thanks, based upon the docs from Intel I've a version up and running now: ---snip--- FreeBSD 5.2-CURRENT #34: Sun Jun 20 21:04:28 CEST 2004 root@M87.Leidinger.net:/system/usr_src/sys/i386/compile/M87 Using 16 colors for the VM-PQ tuning (512, 8) Preloaded elf kernel "/boot/kernel/kernel" at 0xc08a9000. [...] CPU: Intel(R) Pentium(R) 4 CPU 2.40GHz (2405.46-MHz 686-class CPU) Origin = "GenuineIntel" Id = 0xf29 Stepping = 9 Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> Hyperthreading: 2 logical CPUs Extended features=0x4400<CID> Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries 1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size Trace cache: 12K-uops, 8-way set associative 2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size real memory = 1073676288 (1023 MB) ---snip--- >From a feature point of view I don't have anything on my TODO list for this patch (I need to test the universe and fixup some '#if 0' parts). If someone wants to play a little bit with it, it's at http://www.Leidinger.net/FreeBSD/current-patches/pq.diff It should also take a L3 cache into account, if available. It would be nice if someone could review it. I'm not entirely satisfied with the identcpu.c part, but I don't know enough of the big picture of the kernel to provide a cleaner patch. Hints/suggestions are welcome. Bye, Alexander. -- I'm available to get hired (preferred in .lu). http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7
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