Date: Sun, 15 Sep 2019 19:16:42 +0000 (UTC) From: Vladimir Kondratyev <wulf@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r352362 - stable/12/sys/dev/ichiic Message-ID: <201909151916.x8FJGg1A004823@repo.freebsd.org>
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Author: wulf Date: Sun Sep 15 19:16:42 2019 New Revision: 352362 URL: https://svnweb.freebsd.org/changeset/base/352362 Log: ig4(4): Fix SDA HOLD time set too low on Skylake controllers Execution of "Soft reset" command (IG4_REG_RESETS_SKL) at controller init stage sets SDA_HOLD register value to 0x0001 which is often too low for normal operation. Set SDA_HOLD back to 28 after reset to restore controller functionality. PR: 240339 Reported by: imp, GregV, et al. Modified: stable/12/sys/dev/ichiic/ig4_iic.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/ichiic/ig4_iic.c ============================================================================== --- stable/12/sys/dev/ichiic/ig4_iic.c Sun Sep 15 18:29:45 2019 (r352361) +++ stable/12/sys/dev/ichiic/ig4_iic.c Sun Sep 15 19:16:42 2019 (r352362) @@ -590,6 +590,8 @@ ig4iic_attach(ig4iic_softc_t *sc) reg_write(sc, IG4_REG_SS_SCL_LCNT, 125); reg_write(sc, IG4_REG_FS_SCL_HCNT, 100); reg_write(sc, IG4_REG_FS_SCL_LCNT, 125); + if (sc->version == IG4_SKYLAKE) + reg_write(sc, IG4_REG_SDA_HOLD, 28); /* * Use a threshold of 1 so we get interrupted on each character,
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