Date: Fri, 7 May 2004 14:00:06 -0400 From: John Baldwin <jhb@FreeBSD.org> To: freebsd-current@FreeBSD.org Cc: Andrew Gallatin <gallatin@cs.duke.edu> Subject: Re: 4.7 vs 5.2.1 SMP/UP bridging performance Message-ID: <200405071400.06716.jhb@FreeBSD.org> In-Reply-To: <Pine.BSF.4.21.0405061214020.82978-100000@InterJet.elischer.org> References: <Pine.BSF.4.21.0405061214020.82978-100000@InterJet.elischer.org>
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On Thursday 06 May 2004 03:14 pm, Julian Elischer wrote: > On Thu, 6 May 2004, John Baldwin wrote: > > [lots of complicated stuff removed] > > You'd think that intel would have implemented a simple, fast > smp-capable lock primative by now.. cmpxchg isn't that slow on non-P4. :) The membars I described above are basically what you have on sparc9, alpha (alpha's is simpler though), and ia64 as well. It really isn't that complicated since all the magic is in the locking primitives. As long as you properly use the system locking primitives you don't have to worry about this stuff. -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org
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