From owner-freebsd-stable@FreeBSD.ORG Sun Jul 6 17:49:56 2003 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 47DCA37B401 for ; Sun, 6 Jul 2003 17:49:56 -0700 (PDT) Received: from HAL9000.homeunix.com (ip114.bella-vista.sfo.interquest.net [66.199.86.114]) by mx1.FreeBSD.org (Postfix) with ESMTP id 9E64843FB1 for ; Sun, 6 Jul 2003 17:49:55 -0700 (PDT) (envelope-from das@FreeBSD.ORG) Received: from HAL9000.homeunix.com (localhost [127.0.0.1]) by HAL9000.homeunix.com (8.12.9/8.12.9) with ESMTP id h670nqK5027041; Sun, 6 Jul 2003 17:49:52 -0700 (PDT) (envelope-from das@FreeBSD.ORG) Received: (from das@localhost) by HAL9000.homeunix.com (8.12.9/8.12.9/Submit) id h670npQU027040; Sun, 6 Jul 2003 17:49:51 -0700 (PDT) (envelope-from das@FreeBSD.ORG) Date: Sun, 6 Jul 2003 17:49:51 -0700 From: David Schultz To: Chuck Swiger , freebsd-stable@FreeBSD.ORG Message-ID: <20030707004951.GB26820@HAL9000.homeunix.com> Mail-Followup-To: Chuck Swiger , freebsd-stable@freebsd.org References: <200307051728.24681.me@farid-hajji.de> <44brw8g26e.fsf@be-well.ilk.org> <200307060029.00866.me@farid-hajji.de> <3F07576F.4030105@mac.com> <20030706213540.GU430@gsmx07.alcatel.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20030706213540.GU430@gsmx07.alcatel.com.au> Subject: Re: Weird vmstat -s stats X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Jul 2003 00:49:56 -0000 On Mon, Jul 07, 2003, Peter Jeremy wrote: > On 2003-Jul-05 18:55:43 -0400, Chuck Swiger wrote: > >Farid Hajji wrote: > >[ ... ] > >>Shouldn't such counters be at least 64 bit wide? > > > >You betcha. :-) The problem is that a 32-bit CPU, like the Intel x86 > >family, can't increment a 64-bit counter atomicly. > > This isn't absolutely true. You _can_ perform atomic 64-bit > operations on an x86 (for x>=5), they are just extremely expensive. > > There are regular threads on this sort of problem and I don't believe > anyone has come up with a solution that did not involve overheads that > were considered unacceptable in the general case. The overhead of a 64-bit atomic increment isn't so bad on x86. It takes just a few instructions to do the arithmetic (since namei only needs to do increments), plus a cmpxchg8b. But at the moment, we actually use non-atomic increments, which appears to be a bug. We should probably just eat the overhead of 64-bit atomically-incremented counters; the cache_lookup() path isn't so critical that we need every cycle.