Date: Wed, 7 Jun 95 19:22:09 MDT From: terry@cs.weber.edu (Terry Lambert) To: phk@ref.tfs.com (Poul-Henning Kamp) Cc: uhclem%nemesis@fw.ast.com, jgreco@brasil.moneng.mei.com, hackers@FreeBSD.org, bugs@FreeBSD.org Subject: Re: 2.0.5-A: Very disheartening? Message-ID: <9506080122.AA12585@cs.weber.edu> In-Reply-To: <199506080041.RAA04466@ref.tfs.com> from "Poul-Henning Kamp" at Jun 7, 95 05:41:50 pm
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> well, know of any split caches on x386 ? No, though the undocumented cache in the IBM 386 part comes close. > > o All failures of this type have been on Pentium boxes > > o All failures of this type have been on non-Pentium boxes > > None of these are true. So it has happened on both pentium and non-pentium boxes? On the pentium boxes, did disabling only the external (L2) cache help? I heard it did on the 486 boxes. If it didn't on the pentiums, it could be bad cache coherency (ie: an old [pre-APR-1994] chipset). This could be verified for machines that allowed the L2 cache to be enabled when the internal cache was off during the host initiated DMA. > And BTW, the code is loaded into 0x300000..0x3fffff and uncompressed > into 0x100000..0x2fffff Not gate-A20 wrap/"fill in" memory between 640k and 1M-related, then. > And there is a jump to get over there, so the prefetch should be clean. Not necessarily true. Try adding (peeks at his Undocumented PC) 32 NOP's before the jump and see if the problem goes away. The queue is 4/8/16/32 for a 808[86]/286/386/486. Be fun to make it 16 and have it work on 386's but not 486's... 8-). I think the prefetch is *NOT* implicated if the problem occurs on Pentiums with known-good cache coherency and post-APR-1994 masks on the bridge chipsets. If this is the case, the NOPs will do noting, and then it might be interesting to determine if the crash only occurs on PCI/non-PCI boxes or particular BIOS vendors, or other more obscure crap. Terry Lambert terry@cs.weber.edu --- Any opinions in this posting are my own and not those of my present or previous employers.
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