From owner-freebsd-arm@freebsd.org Fri Aug 11 09:35:37 2017 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id A3919DB6C66 for ; Fri, 11 Aug 2017 09:35:37 +0000 (UTC) (envelope-from sylvain@sylvaingarrigues.com) Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5559469C0F for ; Fri, 11 Aug 2017 09:35:37 +0000 (UTC) (envelope-from sylvain@sylvaingarrigues.com) Received: by mail-wm0-x231.google.com with SMTP id i66so42748356wmg.0 for ; Fri, 11 Aug 2017 02:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sylvaingarrigues-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=AobsdKfJxlS/hE8giYteKkqwZrxwGkN4onFFGwADTio=; b=t8bq2FU6kwbxdkddI5V6kvxYOu3s1hGf0+WYDT/CBvNbFy+Cc3KaRq2OL3WWUKUF3N C4R7ZdZLKk4gKw8Bu2Lob6Nlr9aPZOPoAEPFBMjCzje3UvExD4Ff7hoQV0eDkYcsq83q 0nMG2M0juVJ/b5NzYwW1lYbkatMLHjh8YbxxlbcsDE/HpcoxcGX0eVx6vWX/cD/xkruo FWIZDoNjYIzNoBu2K1LiLzKMx5wMyOoW/TmvnMjg4X4GTw5cQdrHsQ1dFf0VvplnCgSw /tSxgUdSTnnmEc1kCMvWIltTq4dBLfjW6INX7l1zgBI+eEyqc2fXIS+4MHXNnnHQB8F4 KxEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=AobsdKfJxlS/hE8giYteKkqwZrxwGkN4onFFGwADTio=; b=lOwUOXRrf9JJm4WdANqXSgLAhi0cPPnvHEW9/kuhWQjOUV1RY4ntfXqkzkBui2uCVG kAwei9cMno9Vm28HVnqTFZ4JyLvj3981PfGKMzPrNWZE1SjKpLDOIUYSAJAOwbOrL9x0 YG7W4tik1DkgiaSNvMOE+RHENIqvP/L+gNEfjlUSDb7V5ITTmDuGzfCaPl8Qkjck5yJC 4YtHixPxA0+Aa9nA3h7INStbKZAoRoUaJzfhuuyw26J1q8y0rZzTPBrpS0eUNnjuUi1R MavAnhaOLEq+k0Y22jqrxE0yxEsaetSVa4Q8nrzMJGUVZz5rCZiEOFnJiiw0awzWSL4C vJDQ== X-Gm-Message-State: AHYfb5hTNSZF6bvoPDuTxqcn1CsdARSKEG78E9hpO5mFYI+S5TW66/D3 0VVdzo1HfFK3dUcfddYYe31JqAJq+xgebSk= X-Received: by 10.80.150.196 with SMTP id z4mr15407250eda.184.1502444135560; Fri, 11 Aug 2017 02:35:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.80.129.229 with HTTP; Fri, 11 Aug 2017 02:35:35 -0700 (PDT) X-Originating-IP: [176.162.147.253] In-Reply-To: <11C8C2C2-02FA-493A-816E-5ED0653EAF78@dsl-only.net> References: <8910A9FB-E936-4576-97B1-B2EDCB1ED1AE@dsl-only.net> <11C8C2C2-02FA-493A-816E-5ED0653EAF78@dsl-only.net> From: Sylvain Garrigues Date: Fri, 11 Aug 2017 11:35:35 +0200 Message-ID: Subject: Re: armv6 kernel support for Raspberry Pi 3 in default aarch32 mode To: Mark Millard Cc: freebsd-arm Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.23 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 09:35:37 -0000 Actually, with latest u-boot and static RPI2 DTB embedded in kernel, I've managed to make the RPI2 kernel boot on my RPI3 and recognize all cortex-a53 processors. I've got errors then because the DTB mustn't be static, the RPI firmware patches it with required values before giving control to kernel. I still need to figure out why the kernel doesn't like the DTB provided by firmware when it's not static, and panics with "OF_init failed with the found device tree" in initarm, but apart from that I feel like we are close to having a 32-bit OS for RPI3 and new RPI2 v1.2. Copyright (c) 1992-2017 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 12.0-CURRENT #45 14d0c5770e7(master)-dirty: Fri Aug 11 17:31:04 CEST 2017 root@box.sylvaingarrigues.com:/usr/obj/arm.armv6/usr/src/sys/GENERIC arm FreeBSD clang version 5.0.0 (branches/release_50 309439) (based on LLVM 5.0.0svn) VT: init without driver. CPU: ARM Cortex-A53 r0p4 (ECO: 0x00000080) CPU Features: Multiprocessing, Thumb2, Security, Virtualization, Generic Timer, VMSAv7, PXN, LPAE, Coherent Walk Optional instructions: SDIV/UDIV, UMULL, SMULL, SIMD(ext) LoUU:2 LoC:3 LoUIS:2 Cache level 1: 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc 32KB/64B 2-way instruction cache Read-Alloc Cache level 2: 512KB/64B 16-way unified cache WB Read-Alloc Write-Alloc ... 2017-08-10 18:04 GMT+02:00 Mark Millard : > On 2017-Aug-10, at 6:51 AM, Sylvain Garrigues sylvaingarrigues.com> wrote: > > > 2017-08-10 1:58 GMT+02:00 Mark Millard : > >> Overall: Supporting aarch32 is not automatic > >> even if one starts from armv7 or specifically > >> a cortex-a53 context unless one was lucky > >> enough to happen to not touch or depend on > >> any of the differences at any stage. > > > > Thanks. I guess though that it's quite easily feasible for someone > familiar with arm lower level initialization. > > > > I can see NetBSD managed to make the armv7 kernel boot on Raspberry Pi 3 > with one commit: > > Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. - > https://github.com/IIJ-NetBSD/netbsd-src/commit/ > 00335f7adc380a125d045279c1a0f5525fb557da > > Interesting. > > > Same for OpenBSD folks: > > http://marc.info/?l=openbsd-tech&m=145692659524971&w=2 > > This one (OpenBSD) says (note the "including some other > (still) local diffs"): > > "This way, and including some other (still) local diffs, I have > the brand new raspberry Pi 3 in multiuser: http://ix.io/oJV " > > So the reference only has some of of the code changes shown. > > And the boot log shows: > > cpu0 at mainbus0: ARM Cortex A53 rev 4 (ARMv7 core) > cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled > cpu0: 32KB(64b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache > > So just one cpu. But for all I know OpenBSD might not have > been SMP capable on a rpi2 at the time either. > > The boot log also shows: > > gpio at bcmgpio0 not configured > broadcom0: device bcmsdhc unit 0 not found > > > So for OpenBSD the code change shown was just the start of the > update as far as I can tell. > > > Plus FreeBSD's RPI2 armv6 kernel does boot and recognize the cortex-a53 > with qemu-aarch64: > > qemu-system-aarch64 -M raspi2 -cpu cortex-a53 -m 1024 -smp 4 -kernel > kernel.bin -serial stdio -dtb rpi2.dtb > > Interesting. How clean is the boot log? > > At least for raspbian there were separate files for rpi3 > when rpi3 was first supported: > > arch/arm/boot/dts/bcm2710-rpi-3-b.dts > arch/arm/boot/dts/bcm2710.dtsi > > Later there was: > > arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts > arch/arm/boot/dts/overlays/pi3-miniuart-bt-overlay.dts > arch/arm/boot/dts/overlays/pi3-disable-wifi-overlay.dts > arch/arm/boot/dts/overlays/pi3-act-led-overlay.dts > > as well as some updates to some of those files. (I'm > not sure that I found all such files that are rpi3 > specific [possibly covering rpi2v1.2 as well?].) > > I suspect the qemu-system-aarch64 use is simulating > a rpi2's details as listed in rpi2.dtb instead of the > rpi3's details. (But using a cortex-a53 CPU model.) > There may well be work in supporting the rpi3's > details in the kernel and/or boot loading stages for > all I know. > > What happens if a rpi3 dtb file is used instead of > rpi2.dtb ? > > > > So I guess we too are really not far to boot RPI2 "armv6" kernel on > raspberry pi 2 v1.2 and raspberry pi 3. > > I wish I could help. > > Since I'm finding these things as I go I've no clue > what I've not found. So I can not tell how close to > correct you are. > > > === > Mark Millard > markmi at dsl-only.net > > > >