Date: Mon, 11 Apr 2005 00:15:33 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: Scott Long <scottl@samsco.org>, Doug White <dwhite@gumbysoft.com>, freebsd-current@freebsd.org Subject: Re: Potential source of interrupt aliasing Message-ID: <200504110715.j3B7FXVK048668@apollo.backplane.com> References: <20050406233405.O47071@carver.gumbysoft.com> <200504081656.51917.jhb@FreeBSD.org> <20050410152946.W82708@carver.gumbysoft.com> <20050410172818.D82708@carver.gumbysoft.com> <200504110231.j3B2VOYr047361@apollo.backplane.com> <425A10DD.70500@samsco.org>
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: Hmm. I can think of two solutions that avoid masking:
:
: * Change the trigger mode from level to edge as a means of masking the
: interrupt, then change it back to level triggered to unmask. This
: would be done in the IO APIC.
:
: * Change the delivery mode to low-priority for the interrupt that occured
: and use the priority field to mask the interrupt to the cpu. This
: would be done in the IO APIC with the LAPIC's TPR set appropriately.
Here's a third... mess with the IOART_DEST mask for the pin on the
IOAPIC. Can it be set to not route the interrupt to *any* cpu ?
Usually it's set to broadcast (all bits 1, at least on 4.x and DragonFly).
so. e.g. IOART_DESTPHY but then with no cpu specified in IOART_DEST.
-Matt
Matthew Dillon
<dillon@backplane.com>
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