Date: Fri, 11 Nov 2016 21:01:46 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308559 - head/contrib/llvm/lib/Target/AArch64 Message-ID: <201611112101.uABL1koq038132@repo.freebsd.org>
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Author: dim Date: Fri Nov 11 21:01:45 2016 New Revision: 308559 URL: https://svnweb.freebsd.org/changeset/base/308559 Log: Pull in r263169 from upstream llvm trunk (by Tim Northover): AArch64: only try to use scaled fcvt ops on legal vector types. Before we ended up calling getSimpleVectorType on a <3 x float>, which asserted. This fixes an assertion when building the print/ghostscript9-agpl-base port for AArch64. PR: 213865 MFC after: 3 days Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Nov 11 20:44:33 2016 (r308558) +++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Nov 11 21:01:45 2016 (r308559) @@ -7581,7 +7581,8 @@ static SDValue performFpToIntCombine(SDN return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || + Op.getOpcode() != ISD::FMUL) return SDValue(); SDValue ConstVec = Op->getOperand(1);
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