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Date:      Thu, 29 Oct 2009 21:14:10 +0000 (UTC)
From:      Randall Stewart <rrs@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-projects@freebsd.org
Subject:   svn commit: r198625 - projects/mips/sys/mips/rmi
Message-ID:  <200910292114.n9TLEAw3009768@svn.freebsd.org>

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Author: rrs
Date: Thu Oct 29 21:14:10 2009
New Revision: 198625
URL: http://svn.freebsd.org/changeset/base/198625

Log:
  White space changes
  
  > Description of fields to fill in above:                     76 columns --|
  > PR:            If a GNATS PR is affected by the change.
  > Submitted by:  If someone else sent in the change.
  > Reviewed by:   If someone else reviewed your modification.
  > Approved by:   If you needed approval for this commit.
  > Obtained from: If the change is from a third party.
  > MFC after:     N [day[s]|week[s]|month[s]].  Request a reminder email.
  > Security:      Vulnerability reference (one per line) or description.
  > Empty fields above will be automatically removed.
  
  M    rmi/xls_ehci.c
  M    rmi/clock.h
  M    rmi/xlr_pci.c
  M    rmi/perfmon.h
  M    rmi/uart_bus_xlr_iodi.c
  M    rmi/perfmon_percpu.c
  M    rmi/iodi.c
  M    rmi/pcibus.c
  M    rmi/perfmon_kern.c
  M    rmi/perfmon_xlrconfig.h
  M    rmi/pcibus.h
  M    rmi/tick.c
  M    rmi/xlr_boot1_console.c
  M    rmi/debug.h
  M    rmi/uart_cpu_mips_xlr.c
  M    rmi/xlrconfig.h
  M    rmi/interrupt.h
  M    rmi/xlr_i2c.c
  M    rmi/shared_structs.h
  M    rmi/msgring.c
  M    rmi/iomap.h
  M    rmi/ehcireg.h
  M    rmi/msgring.h
  M    rmi/shared_structs_func.h
  M    rmi/on_chip.c
  M    rmi/pic.h
  M    rmi/xlr_machdep.c
  M    rmi/ehcivar.h
  M    rmi/board.c
  M    rmi/clock.c
  M    rmi/shared_structs_offsets.h
  M    rmi/perfmon_utils.h
  M    rmi/board.h
  M    rmi/msgring_xls.c
  M    rmi/intr_machdep.c

Modified:
  projects/mips/sys/mips/rmi/board.c
  projects/mips/sys/mips/rmi/board.h
  projects/mips/sys/mips/rmi/clock.c
  projects/mips/sys/mips/rmi/clock.h
  projects/mips/sys/mips/rmi/debug.h
  projects/mips/sys/mips/rmi/ehcireg.h
  projects/mips/sys/mips/rmi/ehcivar.h
  projects/mips/sys/mips/rmi/interrupt.h
  projects/mips/sys/mips/rmi/intr_machdep.c
  projects/mips/sys/mips/rmi/iodi.c
  projects/mips/sys/mips/rmi/iomap.h
  projects/mips/sys/mips/rmi/msgring.c
  projects/mips/sys/mips/rmi/msgring.h
  projects/mips/sys/mips/rmi/msgring_xls.c
  projects/mips/sys/mips/rmi/on_chip.c
  projects/mips/sys/mips/rmi/pcibus.c
  projects/mips/sys/mips/rmi/pcibus.h
  projects/mips/sys/mips/rmi/perfmon.h
  projects/mips/sys/mips/rmi/perfmon_kern.c
  projects/mips/sys/mips/rmi/perfmon_percpu.c
  projects/mips/sys/mips/rmi/perfmon_utils.h
  projects/mips/sys/mips/rmi/perfmon_xlrconfig.h
  projects/mips/sys/mips/rmi/pic.h
  projects/mips/sys/mips/rmi/shared_structs.h
  projects/mips/sys/mips/rmi/shared_structs_func.h
  projects/mips/sys/mips/rmi/shared_structs_offsets.h
  projects/mips/sys/mips/rmi/tick.c
  projects/mips/sys/mips/rmi/uart_bus_xlr_iodi.c
  projects/mips/sys/mips/rmi/uart_cpu_mips_xlr.c
  projects/mips/sys/mips/rmi/xlr_boot1_console.c
  projects/mips/sys/mips/rmi/xlr_i2c.c
  projects/mips/sys/mips/rmi/xlr_machdep.c
  projects/mips/sys/mips/rmi/xlr_pci.c
  projects/mips/sys/mips/rmi/xlrconfig.h
  projects/mips/sys/mips/rmi/xls_ehci.c

Modified: projects/mips/sys/mips/rmi/board.c
==============================================================================
--- projects/mips/sys/mips/rmi/board.c	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/board.c	Thu Oct 29 21:14:10 2009	(r198625)
@@ -41,68 +41,69 @@
 #include <mips/rmi/shared_structs.h>
 
 static int xlr_rxstn_to_txstn_map[128] = {
-	[0 ... 7] = TX_STN_CPU_0,
-	[8 ... 15] = TX_STN_CPU_1,
-	[16 ... 23] = TX_STN_CPU_2,
-	[24 ... 31] = TX_STN_CPU_3,
-	[32 ... 39] = TX_STN_CPU_4,
-	[40 ... 47] = TX_STN_CPU_5,
-	[48 ... 55] = TX_STN_CPU_6,
-	[56 ... 63] = TX_STN_CPU_7,
-	[64 ... 95] = TX_STN_INVALID,
-	[96 ... 103] = TX_STN_GMAC,
-	[104 ... 107] = TX_STN_DMA,
-	[108 ... 111] = TX_STN_INVALID,
-	[112 ... 113] = TX_STN_XGS_0,
-	[114 ... 115] = TX_STN_XGS_1,
-	[116 ... 119] = TX_STN_INVALID,
-	[120 ... 127] = TX_STN_SAE
+	[0...7] = TX_STN_CPU_0,
+	[8...15] = TX_STN_CPU_1,
+	[16...23] = TX_STN_CPU_2,
+	[24...31] = TX_STN_CPU_3,
+	[32...39] = TX_STN_CPU_4,
+	[40...47] = TX_STN_CPU_5,
+	[48...55] = TX_STN_CPU_6,
+	[56...63] = TX_STN_CPU_7,
+	[64...95] = TX_STN_INVALID,
+	[96...103] = TX_STN_GMAC,
+	[104...107] = TX_STN_DMA,
+	[108...111] = TX_STN_INVALID,
+	[112...113] = TX_STN_XGS_0,
+	[114...115] = TX_STN_XGS_1,
+	[116...119] = TX_STN_INVALID,
+	[120...127] = TX_STN_SAE
 };
 
 static int xls_rxstn_to_txstn_map[128] = {
-	[0 ... 7] = TX_STN_CPU_0,
-	[8 ... 15] = TX_STN_CPU_1,
-	[16 ... 23] = TX_STN_CPU_2,
-	[24 ... 31] = TX_STN_CPU_3,
-	[32 ... 63] = TX_STN_INVALID,
-	[64 ... 71] = TX_STN_PCIE,
-	[72 ... 79] = TX_STN_INVALID,
-	[80 ... 87] = TX_STN_GMAC1,
-	[88 ... 95] = TX_STN_INVALID,
-	[96 ... 103] = TX_STN_GMAC0,
-	[104 ... 107] = TX_STN_DMA,
-	[108 ... 111] = TX_STN_CDE,
-	[112 ... 119] = TX_STN_INVALID,
-	[120 ... 127] = TX_STN_SAE
+	[0...7] = TX_STN_CPU_0,
+	[8...15] = TX_STN_CPU_1,
+	[16...23] = TX_STN_CPU_2,
+	[24...31] = TX_STN_CPU_3,
+	[32...63] = TX_STN_INVALID,
+	[64...71] = TX_STN_PCIE,
+	[72...79] = TX_STN_INVALID,
+	[80...87] = TX_STN_GMAC1,
+	[88...95] = TX_STN_INVALID,
+	[96...103] = TX_STN_GMAC0,
+	[104...107] = TX_STN_DMA,
+	[108...111] = TX_STN_CDE,
+	[112...119] = TX_STN_INVALID,
+	[120...127] = TX_STN_SAE
 };
 
 struct stn_cc *xlr_core_cc_configs[] = {&cc_table_cpu_0, &cc_table_cpu_1,
-					&cc_table_cpu_2, &cc_table_cpu_3,
-					&cc_table_cpu_4, &cc_table_cpu_5,
-					&cc_table_cpu_6, &cc_table_cpu_7 };
+	&cc_table_cpu_2, &cc_table_cpu_3,
+	&cc_table_cpu_4, &cc_table_cpu_5,
+&cc_table_cpu_6, &cc_table_cpu_7};
 
-struct stn_cc *xls_core_cc_configs[] =  {&xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
-					  &xls_cc_table_cpu_2, &xls_cc_table_cpu_3};
+struct stn_cc *xls_core_cc_configs[] = {&xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
+&xls_cc_table_cpu_2, &xls_cc_table_cpu_3};
 
 struct xlr_board_info xlr_board_info;
 
 /*
- * All our knowledge of chip and board that cannot be detected by probing 
+ * All our knowledge of chip and board that cannot be detected by probing
  * at run-time goes here
  */
-int xlr_board_info_setup()
+int 
+xlr_board_info_setup()
 {
 	if (xlr_is_xls()) {
 		xlr_board_info.is_xls = 1;
 		xlr_board_info.nr_cpus = 8;
 		xlr_board_info.usb = 1;
 		xlr_board_info.cfi =
-			(xlr_boot1_info.board_major_version !=  RMI_XLR_BOARD_ARIZONA_VIII);
+		    (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
 		xlr_board_info.pci_irq = 0;
 		xlr_board_info.credit_configs = xls_core_cc_configs;
-		xlr_board_info.bucket_sizes   =  &xls_bucket_sizes;
-		xlr_board_info.msgmap         =  xls_rxstn_to_txstn_map;
-		xlr_board_info.gmacports      = 8;
+		xlr_board_info.bucket_sizes = &xls_bucket_sizes;
+		xlr_board_info.msgmap = xls_rxstn_to_txstn_map;
+		xlr_board_info.gmacports = 8;
 
 		/* network block 0 */
 		xlr_board_info.gmac_block[0].type = XLR_GMAC;
@@ -110,13 +111,13 @@ int xlr_board_info_setup()
 		xlr_board_info.gmac_block[0].credit_config = &xls_cc_table_gmac0;
 		xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
 		xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
-		if (xlr_boot1_info.board_major_version ==  RMI_XLR_BOARD_ARIZONA_VI)
+		if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI)
 			xlr_board_info.gmac_block[0].mode = XLR_PORT0_RGMII;
 		else
 			xlr_board_info.gmac_block[0].mode = XLR_SGMII;
-		xlr_board_info.gmac_block[0].baseaddr =  XLR_IO_GMAC_0_OFFSET;
-		xlr_board_info.gmac_block[0].baseirq =  PIC_GMAC_0_IRQ;
-		xlr_board_info.gmac_block[0].baseinst =  0;
+		xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
+		xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
+		xlr_board_info.gmac_block[0].baseinst = 0;
 
 		/* network block 1 */
 		xlr_board_info.gmac_block[1].type = XLR_GMAC;
@@ -124,13 +125,13 @@ int xlr_board_info_setup()
 		xlr_board_info.gmac_block[1].credit_config = &xls_cc_table_gmac1;
 		xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_GMAC1_TX0;
 		xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_GMAC1_FR_0;
-		xlr_board_info.gmac_block[1].mode =  XLR_SGMII;
-		xlr_board_info.gmac_block[1].baseaddr =  XLR_IO_GMAC_4_OFFSET;
-		xlr_board_info.gmac_block[1].baseirq =  PIC_XGS_0_IRQ;
-		xlr_board_info.gmac_block[1].baseinst =  4;
+		xlr_board_info.gmac_block[1].mode = XLR_SGMII;
+		xlr_board_info.gmac_block[1].baseaddr = XLR_IO_GMAC_4_OFFSET;
+		xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
+		xlr_board_info.gmac_block[1].baseinst = 4;
 
 		/* network block 2 */
-		xlr_board_info.gmac_block[2].enabled = 0;  /* disabled on XLS */
+		xlr_board_info.gmac_block[2].enabled = 0;	/* disabled on XLS */
 	} else {
 		xlr_board_info.is_xls = 0;
 		xlr_board_info.nr_cpus = 32;
@@ -138,9 +139,9 @@ int xlr_board_info_setup()
 		xlr_board_info.cfi = 1;
 		xlr_board_info.pci_irq = 0;
 		xlr_board_info.credit_configs = xlr_core_cc_configs;
-		xlr_board_info.bucket_sizes   = &bucket_sizes;
-		xlr_board_info.msgmap         =  xlr_rxstn_to_txstn_map;
-		xlr_board_info.gmacports         = 4;
+		xlr_board_info.bucket_sizes = &bucket_sizes;
+		xlr_board_info.msgmap = xlr_rxstn_to_txstn_map;
+		xlr_board_info.gmacports = 4;
 
 		/* GMAC0 */
 		xlr_board_info.gmac_block[0].type = XLR_GMAC;
@@ -149,9 +150,9 @@ int xlr_board_info_setup()
 		xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
 		xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
 		xlr_board_info.gmac_block[0].mode = XLR_RGMII;
-		xlr_board_info.gmac_block[0].baseaddr =  XLR_IO_GMAC_0_OFFSET;
-		xlr_board_info.gmac_block[0].baseirq =  PIC_GMAC_0_IRQ;
-		xlr_board_info.gmac_block[0].baseinst =  0;
+		xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
+		xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
+		xlr_board_info.gmac_block[0].baseinst = 0;
 
 		/* XGMAC0  */
 		xlr_board_info.gmac_block[1].type = XLR_XGMAC;
@@ -160,9 +161,9 @@ int xlr_board_info_setup()
 		xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_XGS0_TX;
 		xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_XGS0FR;
 		xlr_board_info.gmac_block[1].mode = -1;
-		xlr_board_info.gmac_block[1].baseaddr =  XLR_IO_XGMAC_0_OFFSET;
-		xlr_board_info.gmac_block[1].baseirq =  PIC_XGS_0_IRQ;
-		xlr_board_info.gmac_block[1].baseinst =  4;
+		xlr_board_info.gmac_block[1].baseaddr = XLR_IO_XGMAC_0_OFFSET;
+		xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
+		xlr_board_info.gmac_block[1].baseinst = 4;
 
 		/* XGMAC1 */
 		xlr_board_info.gmac_block[2].type = XLR_XGMAC;
@@ -171,9 +172,9 @@ int xlr_board_info_setup()
 		xlr_board_info.gmac_block[2].station_txbase = MSGRNG_STNID_XGS1_TX;
 		xlr_board_info.gmac_block[2].station_rfr = MSGRNG_STNID_XGS1FR;
 		xlr_board_info.gmac_block[2].mode = -1;
-		xlr_board_info.gmac_block[2].baseaddr =  XLR_IO_XGMAC_1_OFFSET;
-		xlr_board_info.gmac_block[2].baseirq =  PIC_XGS_1_IRQ;
-		xlr_board_info.gmac_block[2].baseinst =  5;
+		xlr_board_info.gmac_block[2].baseaddr = XLR_IO_XGMAC_1_OFFSET;
+		xlr_board_info.gmac_block[2].baseirq = PIC_XGS_1_IRQ;
+		xlr_board_info.gmac_block[2].baseinst = 5;
 	}
 	return 0;
 }

Modified: projects/mips/sys/mips/rmi/board.h
==============================================================================
--- projects/mips/sys/mips/rmi/board.h	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/board.h	Thu Oct 29 21:14:10 2009	(r198625)
@@ -150,7 +150,7 @@ xlr_revision_b0(void)
 static __inline__ int
 xlr_revision_b1(void)
 {
-	return xlr_revision() ==  0x0c0003;
+	return xlr_revision() == 0x0c0003;
 }
 
 static __inline__ int
@@ -182,7 +182,8 @@ static __inline__ int
 xlr_board_atx_iv(void)
 {
 	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
-	&& (xlr_boot1_info.board_minor_version == 0); }
+	&& (xlr_boot1_info.board_minor_version == 0);
+}
 static __inline__ int
 xlr_board_atx_iv_b(void)
 {
@@ -225,48 +226,54 @@ static __inline__ int
 xlr_board_pci(void)
 {
 	return (xlr_board_atx_iii_256() || xlr_board_atx_iii_512()
-		|| xlr_board_atx_v_512());
+	    || xlr_board_atx_v_512());
 }
 static __inline__ int
 xlr_is_xls2xx(void)
 {
-       uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+	uint32_t chipid = mips_rd_prid() & 0xffffff00U;
 
-       return chipid == 0x0c8e00 ||  chipid == 0x0c8f00;
+	return chipid == 0x0c8e00 || chipid == 0x0c8f00;
 }
 
 static __inline__ int
 xlr_is_xls4xx(void)
 {
-       uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+	uint32_t chipid = mips_rd_prid() & 0xffffff00U;
 
-       return chipid == 0x0c8800 ||  chipid == 0x0c8c00;
+	return chipid == 0x0c8800 || chipid == 0x0c8c00;
 }
 
 /* all our knowledge of chip and board that cannot be detected run-time goes here */
-enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
-enum gmac_block_modes { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII };
+enum gmac_block_types {
+	XLR_GMAC, XLR_XGMAC, XLR_SPI4
+};
+enum gmac_block_modes {
+	XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII
+};
 struct xlr_board_info {
 	int is_xls;
 	int nr_cpus;
-	int usb;                               /* usb enabled ? */
-	int cfi;                               /* compact flash driver for NOR? */
+	int usb;		/* usb enabled ? */
+	int cfi;		/* compact flash driver for NOR? */
 	int pci_irq;
-	struct stn_cc **credit_configs;        /* pointer to Core station credits */
-	struct bucket_size *bucket_sizes;      /* pointer to Core station bucket */
-	int *msgmap;                           /* mapping of message station to devices */
-	int gmacports;                         /* number of gmac ports on the board */
+	struct stn_cc **credit_configs;	/* pointer to Core station credits */
+	struct bucket_size *bucket_sizes;	/* pointer to Core station
+						 * bucket */
+	int *msgmap;		/* mapping of message station to devices */
+	int gmacports;		/* number of gmac ports on the board */
 	struct xlr_gmac_block_t {
-		int  type;                     /* see  enum gmac_block_types */
-		unsigned int enabled;          /* mask of ports enabled */   
-		struct stn_cc *credit_config;  /* credit configuration */
-		int station_txbase;            /* station id for tx */
-		int station_rfr;               /* free desc bucket */
-		int  mode;                     /* see gmac_block_modes */
-		uint32_t baseaddr;             /* IO base */
-		int baseirq;        /* first irq for this block, the rest are in sequence */
-		int baseinst;       /* the first rge unit for this block */
-	} gmac_block [3];
+		int type;	/* see  enum gmac_block_types */
+		unsigned int enabled;	/* mask of ports enabled */
+		struct stn_cc *credit_config;	/* credit configuration */
+		int station_txbase;	/* station id for tx */
+		int station_rfr;/* free desc bucket */
+		int mode;	/* see gmac_block_modes */
+		uint32_t baseaddr;	/* IO base */
+		int baseirq;	/* first irq for this block, the rest are in
+				 * sequence */
+		int baseinst;	/* the first rge unit for this block */
+	}                gmac_block[3];
 };
 
 extern struct xlr_board_info xlr_board_info;

Modified: projects/mips/sys/mips/rmi/clock.c
==============================================================================
--- projects/mips/sys/mips/rmi/clock.c	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/clock.c	Thu Oct 29 21:14:10 2009	(r198625)
@@ -28,7 +28,7 @@
  *
  * RMI_BSD */
 
-#include <sys/cdefs.h>      /* RCS ID & Copyright macro defns */
+#include <sys/cdefs.h>		/* RCS ID & Copyright macro defns */
 
 #include <sys/param.h>
 #include <sys/kernel.h>
@@ -77,12 +77,13 @@ u_int32_t counter_lower_last = 0;
 static int scale_factor;
 static int count_scale_factor[32];
 
-uint64_t platform_get_frequency()
+uint64_t 
+platform_get_frequency()
 {
 	return XLR_PIC_HZ;
 }
 
-void 
+void
 mips_timer_early_init(uint64_t clock_hz)
 {
 	/* Initialize clock early so that we can use DELAY sooner */
@@ -94,7 +95,7 @@ mips_timer_early_init(uint64_t clock_hz)
 /*
 * count_compare_clockhandler:
 *
-* Handle the clock interrupt when count becomes equal to 
+* Handle the clock interrupt when count becomes equal to
 * compare.
 */
 void
@@ -107,23 +108,21 @@ count_compare_clockhandler(struct trapfr
 
 	if (cpu == 0) {
 		mips_wr_compare(0);
-	}
-	else {
+	} else {
 		count_scale_factor[cpu]++;
 		cycles = mips_rd_count();
-		cycles += XLR_CPU_HZ/hz;
+		cycles += XLR_CPU_HZ / hz;
 		mips_wr_compare(cycles);
 
 		hardclock_cpu(USERMODE(tf->sr));
 		if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
 			statclock(USERMODE(tf->sr));
-			if(profprocs != 0) {
+			if (profprocs != 0) {
 				profclock(USERMODE(tf->sr), tf->pc);
 			}
 			count_scale_factor[cpu] = 0;
 		}
-
-	/* If needed , handle count compare tick skew here */
+		/* If needed , handle count compare tick skew here */
 	}
 
 	critical_exit();
@@ -141,18 +140,17 @@ pic_hardclockhandler(struct trapframe *t
 		hardclock(USERMODE(tf->sr), tf->pc);
 		if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
 			statclock(USERMODE(tf->sr));
-			if(profprocs != 0) {
+			if (profprocs != 0) {
 				profclock(USERMODE(tf->sr), tf->pc);
 			}
 			scale_factor = 0;
 		}
 #ifdef XLR_PERFMON
 		if (xlr_perfmon_started)
-			xlr_perfmon_clockhandler(); 
+			xlr_perfmon_clockhandler();
 #endif
 
-	}
-	else {
+	} else {
 		/* If needed , handle count compare tick skew here */
 	}
 	critical_exit();
@@ -161,75 +159,77 @@ pic_hardclockhandler(struct trapframe *t
 int
 pic_timecounthandler(struct trapframe *tf)
 {
-  return (FILTER_HANDLED);
+	return (FILTER_HANDLED);
 }
 
 void
 platform_initclocks(void)
 {
-  int cpu = PCPU_GET(cpuid);
-  void *cookie;
+	int cpu = PCPU_GET(cpuid);
+	void *cookie;
 
-  /* Note: Passing #3 as NULL ensures that clockhandler 
-   * gets called with trapframe 
-   */
-  /* profiling/process accounting timer interrupt for non-zero cpus */
-  cpu_establish_hardintr("compare", 
-						 NULL,
-						 (driver_intr_t *)count_compare_clockhandler,
-						 NULL,
-						 IRQ_TIMER, 
-						 INTR_TYPE_CLK|INTR_FAST, &cookie);
-
-  /* timekeeping timer interrupt for cpu 0 */
-  cpu_establish_hardintr("hardclk", 
-						 NULL,
-						 (driver_intr_t *)pic_hardclockhandler,
-						 NULL,
-						 PIC_TIMER_7_IRQ,
-						 INTR_TYPE_CLK|INTR_FAST,
-						 &cookie);
-
-  /* this is used by timecounter */
-   cpu_establish_hardintr("timecount", 
-						  (driver_filter_t *)pic_timecounthandler, NULL,
-						  NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK|INTR_FAST,
-						  &cookie);
-   	
-  if (cpu == 0) {
-	__uint64_t maxval = XLR_PIC_HZ/hz;
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+	/*
+	 * Note: Passing #3 as NULL ensures that clockhandler gets called
+	 * with trapframe
+	 */
+	/* profiling/process accounting timer interrupt for non-zero cpus */
+	cpu_establish_hardintr("compare",
+	    NULL,
+	    (driver_intr_t *) count_compare_clockhandler,
+	    NULL,
+	    IRQ_TIMER,
+	    INTR_TYPE_CLK | INTR_FAST, &cookie);
+
+	/* timekeeping timer interrupt for cpu 0 */
+	cpu_establish_hardintr("hardclk",
+	    NULL,
+	    (driver_intr_t *) pic_hardclockhandler,
+	    NULL,
+	    PIC_TIMER_7_IRQ,
+	    INTR_TYPE_CLK | INTR_FAST,
+	    &cookie);
+
+	/* this is used by timecounter */
+	cpu_establish_hardintr("timecount",
+	    (driver_filter_t *) pic_timecounthandler, NULL,
+	    NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK | INTR_FAST,
+	    &cookie);
+
+	if (cpu == 0) {
+		__uint64_t maxval = XLR_PIC_HZ / hz;
+		xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 
-	stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
-	profhz = stathz;
+		stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
+		profhz = stathz;
 
-	/* Setup PIC Interrupt */
+		/* Setup PIC Interrupt */
 
-	mtx_lock_spin(&xlr_pic_lock);
-	xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7*/
-	xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff);/* 0x110 + 7 */
-	/* 0x40 + 8 */
-	/* reg 40 is lower bits 31-0  and holds CPU mask */
-	xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
-	/* 0x80 + 8 */
-	/* Reg 80 is upper bits 63-32 and holds                              */
-	/*                                      Valid   Edge    Local    IRQ */
-	xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_7_IRQ)); 
-	pic_update_control(1<<(8+7));
-
-	xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
-	xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
-	xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
-	xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_6_IRQ));
-	pic_update_control(1<<(8+6));
-	mtx_unlock_spin(&xlr_pic_lock);
-  } else {
-	/* Setup count-compare interrupt for vcpu[1-31] */
-	mips_wr_compare((xlr_boot1_info.cpu_frequency)/hz);
-  }
+		mtx_lock_spin(&xlr_pic_lock);
+		xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff));	/* 0x100 + 7 */
+		xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff);	/* 0x110 + 7 */
+		/* 0x40 + 8 */
+		/* reg 40 is lower bits 31-0  and holds CPU mask */
+		xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
+		/* 0x80 + 8 */
+		/* Reg 80 is upper bits 63-32 and holds                              */
+		/* Valid   Edge    Local    IRQ */
+		xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_7_IRQ));
+		pic_update_control(1 << (8 + 7));
+
+		xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
+		xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
+		xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
+		xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
+		pic_update_control(1 << (8 + 6));
+		mtx_unlock_spin(&xlr_pic_lock);
+	} else {
+		/* Setup count-compare interrupt for vcpu[1-31] */
+		mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
+	}
 }
 
-unsigned __attribute__((no_instrument_function))
+unsigned 
+__attribute__((no_instrument_function))
 platform_get_timecount(struct timecounter *tc __unused)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
@@ -268,18 +268,21 @@ DELAY(int n)
 }
 
 static
-uint64_t read_pic_counter(void)
+uint64_t 
+read_pic_counter(void)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 	uint32_t lower, upper;
 	uint64_t tc;
-	/* Pull the value of the 64 bit counter which is stored in
-	 * PIC register 120+N and 130+N
+
+	/*
+	 * Pull the value of the 64 bit counter which is stored in PIC
+	 * register 120+N and 130+N
 	 */
-	upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);  
+	upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
 	lower = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
-	tc = (((uint64_t)upper << 32) | (uint64_t)lower);
-	return(tc);
+	tc = (((uint64_t) upper << 32) | (uint64_t) lower);
+	return (tc);
 }
 
 extern struct timecounter counter_timecounter;
@@ -303,16 +306,16 @@ mips_timer_init_params(uint64_t platform
 	cycles_per_tick = counter_freq / 1000;
 	cycles_per_hz = counter_freq / hz;
 	cycles_per_usec = counter_freq / (1 * 1000 * 1000);
-	cycles_per_sec =  counter_freq ;
-	
+	cycles_per_sec = counter_freq;
+
 	counter_timecounter.tc_frequency = counter_freq;
 	printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n",
-	       hz,
-	       cycles_per_tick,
-	       cycles_per_usec,
-	       counter_freq,
-	       cycles_per_hz,
-	       cycles_per_sec
-	       );
+	    hz,
+	    cycles_per_tick,
+	    cycles_per_usec,
+	    counter_freq,
+	    cycles_per_hz,
+	    cycles_per_sec
+	    );
 	set_cputicker(read_pic_counter, counter_freq, 1);
 }

Modified: projects/mips/sys/mips/rmi/clock.h
==============================================================================
--- projects/mips/sys/mips/rmi/clock.h	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/clock.h	Thu Oct 29 21:14:10 2009	(r198625)
@@ -37,4 +37,4 @@ void count_compare_clockhandler(struct t
 void pic_hardclockhandler(struct trapframe *);
 int pic_timecounthandler(struct trapframe *);
 
-#endif /* _RMI_CLOCK_H_ */
+#endif				/* _RMI_CLOCK_H_ */

Modified: projects/mips/sys/mips/rmi/debug.h
==============================================================================
--- projects/mips/sys/mips/rmi/debug.h	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/debug.h	Thu Oct 29 21:14:10 2009	(r198625)
@@ -33,51 +33,51 @@
 #include <machine/atomic.h>
 
 enum {
-  //cacheline 0
-  MSGRNG_INT,
-  MSGRNG_PIC_INT,
-  MSGRNG_MSG,
-  MSGRNG_EXIT_STATUS,
-  MSGRNG_MSG_CYCLES,
-  //cacheline 1
-  NETIF_TX = 8,
-  NETIF_RX,
-  NETIF_TX_COMPLETE,
-  NETIF_TX_COMPLETE_TX,
-  NETIF_RX_CYCLES,
-  NETIF_TX_COMPLETE_CYCLES,
-  NETIF_TX_CYCLES,
-  NETIF_TIMER_START_Q,
-  //NETIF_REG_FRIN,
-  //NETIF_INT_REG,
-  //cacheline 2
-  REPLENISH_ENTER = 16,
-  REPLENISH_ENTER_COUNT,
-  REPLENISH_CPU,
-  REPLENISH_FRIN,
-  REPLENISH_CYCLES,
-  NETIF_STACK_TX,
-  NETIF_START_Q,
-  NETIF_STOP_Q,
-  //cacheline 3
-  USER_MAC_START = 24,
-  USER_MAC_INT   = 24,
-  USER_MAC_TX_COMPLETE,
-  USER_MAC_RX,
-  USER_MAC_POLL,
-  USER_MAC_TX,
-  USER_MAC_TX_FAIL,
-  USER_MAC_TX_COUNT,
-  USER_MAC_FRIN,
-  //cacheline 4
-  USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
-  USER_MAC_DO_PAGE_FAULT,
-  USER_MAC_UPDATE_TLB,
-  USER_MAC_UPDATE_BIGTLB,
-  USER_MAC_UPDATE_TLB_PFN0,
-  USER_MAC_UPDATE_TLB_PFN1,
-  
-  XLR_MAX_COUNTERS = 40
+	//cacheline 0
+	MSGRNG_INT,
+	MSGRNG_PIC_INT,
+	MSGRNG_MSG,
+	MSGRNG_EXIT_STATUS,
+	MSGRNG_MSG_CYCLES,
+	//cacheline 1
+	NETIF_TX = 8,
+	NETIF_RX,
+	NETIF_TX_COMPLETE,
+	NETIF_TX_COMPLETE_TX,
+	NETIF_RX_CYCLES,
+	NETIF_TX_COMPLETE_CYCLES,
+	NETIF_TX_CYCLES,
+	NETIF_TIMER_START_Q,
+	//NETIF_REG_FRIN,
+	//NETIF_INT_REG,
+	//cacheline 2
+	REPLENISH_ENTER = 16,
+	REPLENISH_ENTER_COUNT,
+	REPLENISH_CPU,
+	REPLENISH_FRIN,
+	REPLENISH_CYCLES,
+	NETIF_STACK_TX,
+	NETIF_START_Q,
+	NETIF_STOP_Q,
+	//cacheline 3
+	USER_MAC_START = 24,
+	USER_MAC_INT = 24,
+	USER_MAC_TX_COMPLETE,
+	USER_MAC_RX,
+	USER_MAC_POLL,
+	USER_MAC_TX,
+	USER_MAC_TX_FAIL,
+	USER_MAC_TX_COUNT,
+	USER_MAC_FRIN,
+	//cacheline 4
+	USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
+	USER_MAC_DO_PAGE_FAULT,
+	USER_MAC_UPDATE_TLB,
+	USER_MAC_UPDATE_BIGTLB,
+	USER_MAC_UPDATE_TLB_PFN0,
+	USER_MAC_UPDATE_TLB_PFN1,
+
+	XLR_MAX_COUNTERS = 40
 };
 extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS];
 extern __uint32_t msgrng_msg_cycles;
@@ -88,7 +88,7 @@ extern __uint32_t msgrng_msg_cycles;
 #define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value))
 #define xlr_get_counter(x) (&xlr_counters[0][(x)])
 
-#else /* default mode */
+#else				/* default mode */
 
 #define xlr_inc_counter(x)
 #define xlr_dec_counter(x)

Modified: projects/mips/sys/mips/rmi/ehcireg.h
==============================================================================
--- projects/mips/sys/mips/rmi/ehcireg.h	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/ehcireg.h	Thu Oct 29 21:14:10 2009	(r198625)
@@ -60,7 +60,7 @@
 #define  PCI_USBREV_1_1		0x11
 #define  PCI_USBREV_2_0		0x20
 
-#define PCI_EHCI_FLADJ		0x61	/*RW Frame len adj, SOF=59488+6*fladj */
+#define PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
 
 #define PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
 
@@ -77,30 +77,30 @@
 
 /*** EHCI capability registers ***/
 
-#define EHCI_CAPLENGTH		0x00	/*RO Capability register length field */
+#define EHCI_CAPLENGTH		0x00	/* RO Capability register length field */
 /* reserved			0x01 */
 #define EHCI_HCIVERSION		0x02	/* RO Interface version number */
 
 #define EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
 #define  EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
-#define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf) /* # of companion ctlrs */
-#define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf) /* # of ports per comp. */
-#define  EHCI_HCS_PPC(x)	((x) & 0x10) /* port power control */
-#define  EHCI_HCS_N_PORTS(x)	((x) & 0xf) /* # of ports */
+#define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf)	/* # of companion ctlrs */
+#define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf)	/* # of ports per comp. */
+#define  EHCI_HCS_PPC(x)	((x) & 0x10)	/* port power control */
+#define  EHCI_HCS_N_PORTS(x)	((x) & 0xf)	/* # of ports */
 
 #define EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
-#define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff) /* extended ports caps */
-#define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf) /* isoc sched threshold */
-#define  EHCI_HCC_ASPC(x)	((x) & 0x4) /* async sched park cap */
-#define  EHCI_HCC_PFLF(x)	((x) & 0x2) /* prog frame list flag */
-#define  EHCI_HCC_64BIT(x)	((x) & 0x1) /* 64 bit address cap */
+#define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff)	/* extended ports caps */
+#define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf)	/* isoc sched threshold */
+#define  EHCI_HCC_ASPC(x)	((x) & 0x4)	/* async sched park cap */
+#define  EHCI_HCC_PFLF(x)	((x) & 0x2)	/* prog frame list flag */
+#define  EHCI_HCC_64BIT(x)	((x) & 0x1)	/* 64 bit address cap */
 
-#define EHCI_HCSP_PORTROUTE	0x0c	/*RO Companion port route description */
+#define EHCI_HCSP_PORTROUTE	0x0c	/* RO Companion port route description */
 
 /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
 #define EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
-#define  EHCI_CMD_ITC_M		0x00ff0000 /* RW interrupt threshold ctrl */
+#define  EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
 #define   EHCI_CMD_ITC_1	0x00010000
 #define   EHCI_CMD_ITC_2	0x00020000
 #define   EHCI_CMD_ITC_4	0x00040000
@@ -108,39 +108,41 @@
 #define   EHCI_CMD_ITC_16	0x00100000
 #define   EHCI_CMD_ITC_32	0x00200000
 #define   EHCI_CMD_ITC_64	0x00400000
-#define  EHCI_CMD_ASPME		0x00000800 /* RW/RO async park enable */
-#define  EHCI_CMD_ASPMC		0x00000300 /* RW/RO async park count */
-#define  EHCI_CMD_LHCR		0x00000080 /* RW light host ctrl reset */
-#define  EHCI_CMD_IAAD		0x00000040 /* RW intr on async adv door bell */
-#define  EHCI_CMD_ASE		0x00000020 /* RW async sched enable */
-#define  EHCI_CMD_PSE		0x00000010 /* RW periodic sched enable */
-#define  EHCI_CMD_FLS_M		0x0000000c /* RW/RO frame list size */
-#define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3) /* RW/RO frame list size */
-#define  EHCI_CMD_HCRESET	0x00000002 /* RW reset */
-#define  EHCI_CMD_RS		0x00000001 /* RW run/stop */
+#define  EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
+#define  EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
+#define  EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
+#define  EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
+						 * bell */
+#define  EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
+#define  EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
+#define  EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
+#define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3)	/* RW/RO frame list size */
+#define  EHCI_CMD_HCRESET	0x00000002	/* RW reset */
+#define  EHCI_CMD_RS		0x00000001	/* RW run/stop */
 
 #define EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
-#define  EHCI_STS_ASS		0x00008000 /* RO async sched status */
-#define  EHCI_STS_PSS		0x00004000 /* RO periodic sched status */
-#define  EHCI_STS_REC		0x00002000 /* RO reclamation */
-#define  EHCI_STS_HCH		0x00001000 /* RO host controller halted */
-#define  EHCI_STS_IAA		0x00000020 /* RWC interrupt on async adv */
-#define  EHCI_STS_HSE		0x00000010 /* RWC host system error */
-#define  EHCI_STS_FLR		0x00000008 /* RWC frame list rollover */
-#define  EHCI_STS_PCD		0x00000004 /* RWC port change detect */
-#define  EHCI_STS_ERRINT	0x00000002 /* RWC error interrupt */
-#define  EHCI_STS_INT		0x00000001 /* RWC interrupt */
+#define  EHCI_STS_ASS		0x00008000	/* RO async sched status */
+#define  EHCI_STS_PSS		0x00004000	/* RO periodic sched status */
+#define  EHCI_STS_REC		0x00002000	/* RO reclamation */
+#define  EHCI_STS_HCH		0x00001000	/* RO host controller halted */
+#define  EHCI_STS_IAA		0x00000020	/* RWC interrupt on async adv */
+#define  EHCI_STS_HSE		0x00000010	/* RWC host system error */
+#define  EHCI_STS_FLR		0x00000008	/* RWC frame list rollover */
+#define  EHCI_STS_PCD		0x00000004	/* RWC port change detect */
+#define  EHCI_STS_ERRINT	0x00000002	/* RWC error interrupt */
+#define  EHCI_STS_INT		0x00000001	/* RWC interrupt */
 #define  EHCI_STS_INTRS(x)	((x) & 0x3f)
 
 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
 
 #define EHCI_USBINTR		0x08	/* RW Interrupt register */
-#define EHCI_INTR_IAAE		0x00000020 /* interrupt on async advance ena */
-#define EHCI_INTR_HSEE		0x00000010 /* host system error ena */
-#define EHCI_INTR_FLRE		0x00000008 /* frame list rollover ena */
-#define EHCI_INTR_PCIE		0x00000004 /* port change ena */
-#define EHCI_INTR_UEIE		0x00000002 /* USB error intr ena */
-#define EHCI_INTR_UIE		0x00000001 /* USB intr ena */
+#define EHCI_INTR_IAAE		0x00000020	/* interrupt on async advance
+						 * ena */
+#define EHCI_INTR_HSEE		0x00000010	/* host system error ena */
+#define EHCI_INTR_FLRE		0x00000008	/* frame list rollover ena */
+#define EHCI_INTR_PCIE		0x00000004	/* port change ena */
+#define EHCI_INTR_UEIE		0x00000002	/* USB error intr ena */
+#define EHCI_INTR_UIE		0x00000001	/* USB intr ena */
 
 #define EHCI_FRINDEX		0x0c	/* RW Frame Index register */
 
@@ -150,30 +152,30 @@
 #define EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
 
 #define EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
-#define  EHCI_CONF_CF		0x00000001 /* RW configure flag */
+#define  EHCI_CONF_CF		0x00000001	/* RW configure flag */
 
-#define EHCI_PORTSC(n)		(0x40+4*(n)) /* RO, RW, RWC Port Status reg */
-#define  EHCI_PS_WKOC_E		0x00400000 /* RW wake on over current ena */
-#define  EHCI_PS_WKDSCNNT_E	0x00200000 /* RW wake on disconnect ena */
-#define  EHCI_PS_WKCNNT_E	0x00100000 /* RW wake on connect ena */
-#define  EHCI_PS_PTC		0x000f0000 /* RW port test control */
-#define  EHCI_PS_PIC		0x0000c000 /* RW port indicator control */
-#define  EHCI_PS_PO		0x00002000 /* RW port owner */
-#define  EHCI_PS_PP		0x00001000 /* RW,RO port power */
-#define  EHCI_PS_LS		0x00000c00 /* RO line status */
+#define EHCI_PORTSC(n)		(0x40+4*(n))	/* RO, RW, RWC Port Status reg */
+#define  EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
+#define  EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
+#define  EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
+#define  EHCI_PS_PTC		0x000f0000	/* RW port test control */
+#define  EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
+#define  EHCI_PS_PO		0x00002000	/* RW port owner */
+#define  EHCI_PS_PP		0x00001000	/* RW,RO port power */
+#define  EHCI_PS_LS		0x00000c00	/* RO line status */
 #define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
-#define  EHCI_PS_PR		0x00000100 /* RW port reset */
-#define  EHCI_PS_SUSP		0x00000080 /* RW suspend */
-#define  EHCI_PS_FPR		0x00000040 /* RW force port resume */
-#define  EHCI_PS_OCC		0x00000020 /* RWC over current change */
-#define  EHCI_PS_OCA		0x00000010 /* RO over current active */
-#define  EHCI_PS_PEC		0x00000008 /* RWC port enable change */
-#define  EHCI_PS_PE		0x00000004 /* RW port enable */
-#define  EHCI_PS_CSC		0x00000002 /* RWC connect status change */
-#define  EHCI_PS_CS		0x00000001 /* RO connect status */
+#define  EHCI_PS_PR		0x00000100	/* RW port reset */
+#define  EHCI_PS_SUSP		0x00000080	/* RW suspend */
+#define  EHCI_PS_FPR		0x00000040	/* RW force port resume */
+#define  EHCI_PS_OCC		0x00000020	/* RWC over current change */
+#define  EHCI_PS_OCA		0x00000010	/* RO over current active */
+#define  EHCI_PS_PEC		0x00000008	/* RWC port enable change */
+#define  EHCI_PS_PE		0x00000004	/* RW port enable */
+#define  EHCI_PS_CSC		0x00000002	/* RWC connect status change */
+#define  EHCI_PS_CS		0x00000001	/* RO connect status */
 #define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
 
-#define EHCI_PORT_RESET_COMPLETE 2 /* ms */
+#define EHCI_PORT_RESET_COMPLETE 2	/* ms */
 
 #define EHCI_FLALIGN_ALIGN	0x1000
 
@@ -186,6 +188,7 @@
 #endif
 
 typedef u_int32_t ehci_link_t;
+
 #define EHCI_LINK_TERMINATE	0x00000001
 #define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
 #define  EHCI_LINK_ITD		0x0
@@ -198,24 +201,26 @@ typedef u_int32_t ehci_physaddr_t;
 
 /* Isochronous Transfer Descriptor */
 typedef struct {
-	ehci_link_t	itd_next;
+	ehci_link_t itd_next;
 	/* XXX many more */
-} ehci_itd_t;
+}      ehci_itd_t;
+
 #define EHCI_ITD_ALIGN 32
 
 /* Split Transaction Isochronous Transfer Descriptor */
 typedef struct {
-	ehci_link_t	sitd_next;
+	ehci_link_t sitd_next;
 	/* XXX many more */
-} ehci_sitd_t;
+}      ehci_sitd_t;
+
 #define EHCI_SITD_ALIGN 32
 
 /* Queue Element Transfer Descriptor */
 #define EHCI_QTD_NBUFFERS 5
 typedef struct {
-	ehci_link_t	qtd_next;
-	ehci_link_t	qtd_altnext;
-	u_int32_t	qtd_status;
+	ehci_link_t qtd_next;
+	ehci_link_t qtd_altnext;
+	u_int32_t qtd_status;
 #define EHCI_QTD_GET_STATUS(x)	(((x) >>  0) & 0xff)
 #define EHCI_QTD_SET_STATUS(x) ((x) <<  0)
 #define  EHCI_QTD_ACTIVE	0x80
@@ -243,59 +248,62 @@ typedef struct {
 #define EHCI_QTD_GET_TOGGLE(x)	(((x) >> 31) &  0x1)
 #define	EHCI_QTD_SET_TOGGLE(x)	((x) << 31)
 #define EHCI_QTD_TOGGLE_MASK	0x80000000
-	ehci_physaddr_t	qtd_buffer[EHCI_QTD_NBUFFERS];
+	ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
 	ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
-} ehci_qtd_t;
+}      ehci_qtd_t;
+
 #define EHCI_QTD_ALIGN 32
 
 /* Queue Head */
 typedef struct {
-	ehci_link_t	qh_link;
-	u_int32_t	qh_endp;
-#define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f) /* endpoint addr */
+	ehci_link_t qh_link;
+	u_int32_t qh_endp;
+#define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f)	/* endpoint addr */
 #define EHCI_QH_SET_ADDR(x)	(x)
 #define EHCI_QH_ADDRMASK	0x0000007f
-#define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01) /* inactivate on next */
+#define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01)	/* inactivate on next */
 #define EHCI_QH_INACT		0x00000080
-#define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f) /* endpoint no */
+#define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f)	/* endpoint no */
 #define EHCI_QH_SET_ENDPT(x)	((x) <<  8)
-#define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03) /* endpoint speed */
+#define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03)	/* endpoint speed */
 #define EHCI_QH_SET_EPS(x)	((x) << 12)
 #define  EHCI_QH_SPEED_FULL	0x0
 #define  EHCI_QH_SPEED_LOW	0x1
 #define  EHCI_QH_SPEED_HIGH	0x2
-#define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01) /* data toggle control */
+#define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01)	/* data toggle control */
 #define EHCI_QH_DTC		0x00004000
-#define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01) /* head of reclamation */
+#define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01)	/* head of reclamation */
 #define EHCI_QH_HRECL		0x00008000
-#define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff) /* max packet len */
+#define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff)	/* max packet len */
 #define EHCI_QH_SET_MPL(x)	((x) << 16)
 #define EHCI_QH_MPLMASK		0x07ff0000
-#define EHCI_QH_GET_CTL(x)	(((x) >> 27) & 0x01) /* control endpoint */
+#define EHCI_QH_GET_CTL(x)	(((x) >> 27) & 0x01)	/* control endpoint */
 #define EHCI_QH_CTL		0x08000000
-#define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f) /* NAK reload */
+#define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f)	/* NAK reload */
 #define EHCI_QH_SET_NRL(x)	((x) << 28)
-	u_int32_t	qh_endphub;
-#define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff) /* intr sched mask */
+	u_int32_t qh_endphub;
+#define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff)	/* intr sched mask */
 #define EHCI_QH_SET_SMASK(x)	((x) <<  0)
-#define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff) /* split completion mask */
+#define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff)	/* split completion mask */
 #define EHCI_QH_SET_CMASK(x)	((x) <<  8)
-#define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f) /* hub address */
+#define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f)	/* hub address */
 #define EHCI_QH_SET_HUBA(x)	((x) << 16)
-#define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f) /* hub port */
+#define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f)	/* hub port */
 #define EHCI_QH_SET_PORT(x)	((x) << 23)
-#define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03) /* pipe multiplier */
+#define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03)	/* pipe multiplier */
 #define EHCI_QH_SET_MULT(x)	((x) << 30)
-	ehci_link_t	qh_curqtd;
-	ehci_qtd_t	qh_qtd;
-} ehci_qh_t;
+	ehci_link_t qh_curqtd;
+	ehci_qtd_t qh_qtd;
+}      ehci_qh_t;
+
 #define EHCI_QH_ALIGN 32
 
 /* Periodic Frame Span Traversal Node */
 typedef struct {
-	ehci_link_t	fstn_link;
-	ehci_link_t	fstn_back;
-} ehci_fstn_t;
+	ehci_link_t fstn_link;
+	ehci_link_t fstn_back;
+}      ehci_fstn_t;
+
 #define EHCI_FSTN_ALIGN 32
 
-#endif /* _DEV_PCI_EHCIREG_H_ */
+#endif				/* _DEV_PCI_EHCIREG_H_ */

Modified: projects/mips/sys/mips/rmi/ehcivar.h
==============================================================================
--- projects/mips/sys/mips/rmi/ehcivar.h	Thu Oct 29 21:13:57 2009	(r198624)
+++ projects/mips/sys/mips/rmi/ehcivar.h	Thu Oct 29 21:14:10 2009	(r198625)
@@ -39,12 +39,13 @@

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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