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Date:      Mon, 4 Dec 1995 13:54:31 -0700 (MST)
From:      Terry Lambert <>
To: (Robert A. Buaas)
Subject:   Re: Cyrix CPU kernel help
Message-ID:  <>
In-Reply-To: <> from "Robert A. Buaas" at Dec 3, 95 03:17:57 pm

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> I'm having trouble with using a Cyrix 486DX2-80 CPU with the
> 2.1.0-RELEASE kernel. It won't recompile the GENERIC kernel (random
> error 1 stops), and halt/reboot complains about "keyboard restart
> failed, halting CPU". When the system harddrive is moved to another
> system, everything works fine (AMD CPU). When I set the options flag
> "CYRIX_CACHE_WORKS", the kernel compile fails on trying to compile
> locore.s at line 427 (statement is "andl $~(CR0_CD|CR0_NW),%eax" with
> the message "Unimplemented segment type 6 in parse_operand"...
> Any suggestions from your locore isa wizards?

Older mask designs for Cyrix (and TI) processors did not correctly
support cache invalidation for memory locations written by other
than the host processor (ie: bus mastering devices, like SCSI).  It
is an error to set "CYRIX_CACHE_WORKS" on these machines (or if you
ask Cyrix, it's an error to use bus mastering devices, ever).

The compilation failure you are having looks similar to one I had
when I was first trying to integrate Jack Vogel's SMP patches into
my "-current + Terry's patches" kernel.

It turns out that this is the error you will get on a #define'd
assembly macro with a space or tab following the "\" continuation

					Terry Lambert
Any opinions in this posting are my own and not those of my present
or previous employers.

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