Date: Fri, 17 Jan 1997 01:14:15 -0700 From: Steve Passe <smp@csn.net> To: smp@FreeBSD.ORG Subject: Re: Adaptec 3940UW and SMP Message-ID: <199701170814.BAA16113@clem.systemsix.com> In-Reply-To: Your message of "Fri, 17 Jan 1997 00:26:39 MST." <199701170726.AAA15776@clem.systemsix.com>
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Hi, > so this is where I get a little confused... I thought in the past the > typical board limitation of 4 PCI slots was based on the LINE[ABCD] > situation. Early PCI MBs sometimes used LINEA for slot1, LINEB for > slot2, etc. I was thinking that now they route the LINEA pin from each > card to the LINE[ABCD] inputs of the PCI_ISA bridge chip, hence the magic > of the number 4. Is this so, or do these PCI slot/LINEA INTs go directly > to the MB ISA redirector hardware? If so, what is magic about 4 (slots)? > Stated another way, why does the 5th slot need to be shared? doing some research I have concluded that the magic about '4' is that all the chipsets (Neptune,Triton,Natoma) have exactly 4 PCI-ISA redirection registers on them, probably because of the PCI LINE[ABCD] design. So they can only redirect to 4 distinct targets, requireing the "merging" of INTs when getting to slot 5 and above. I suspect that in all other areas it is really a unique PCI slot (wishful thinking?) Whether this limitation applies to the APIC I still don't know... When Peter and I were first getting his EISA disk controller working our experiments as to programming the redirector for edge/level, etc. were very confusing and inconclusive. If anyone has any insight to the specifics of the redirector/APIC connections on the MB, I would love to hear them. -- Steve Passe | powered by smp@csn.net | FreeBSD
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