From owner-freebsd-mips@FreeBSD.ORG Thu Sep 29 06:21:22 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2A1E9106566B; Thu, 29 Sep 2011 06:21:22 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx1.freebsd.org (Postfix) with ESMTP id 89B4B8FC20; Thu, 29 Sep 2011 06:21:21 +0000 (UTC) Received: by wwe3 with SMTP id 3so408576wwe.31 for ; Wed, 28 Sep 2011 23:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=+QdIwXE5tlMEE+fJxbxZ2KFBvpm7FeorQUcsL7f13oM=; b=LP8mev/nxMmM1JDgm1wf0LXSfi37APlcYjMnJScT7NYn2nfL2zLtxtxMJBqVS4l9Mh yQhDSaYh6tlCo2iepc9s02ZAzjxtlxyak1mOGlyBb26mt9cTs0qOHkiqE1PAoPX2G3sw on8nH+3KGrEHFV6HJ5OBlS81hdoPKAefH2414= MIME-Version: 1.0 Received: by 10.216.131.225 with SMTP id m75mr882931wei.1.1317275963529; Wed, 28 Sep 2011 22:59:23 -0700 (PDT) Received: by 10.216.154.5 with HTTP; Wed, 28 Sep 2011 22:59:23 -0700 (PDT) In-Reply-To: References: Date: Thu, 29 Sep 2011 11:29:23 +0530 Message-ID: From: "Jayachandran C." To: Adrian Chadd Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: eventtimer issue on mips: temporary workaround X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Sep 2011 06:21:22 -0000 On Wed, Sep 28, 2011 at 8:14 PM, Adrian Chadd wrote: > Hi all, > > I've found that there's an issue with how mav@ shoehorned in event > timer handling to mips. > > Basically, if a non-fast interrupt comes in after the critical_enter() > call in cpu_idle() but before the wait instruction, it won't interrupt > wait and it won't be serviced until the next interrupt ends the wait. > > For ath, since it's a netisr, this means the netisr won't be run until > the next interrupt fires. > > Here's my temporary, not-quite-correct workaround. ray@ pointed out > this from Linux: > > http://lxr.free-electrons.com/source/arch/mips/kernel/cpu-probe.c?a=3Dsh > > .. which indicates that they're calling wait with interrupts masked. > This apparently doesn't stop it breaking wait, it merely stops it from > flipping to the interrupt handler. Linux has many versions of wait, there is the r4k_wait in assembly which keeps the interrupts enabled http://lxr.free-electrons.com/source/arch/mips/kernel/genex.S#L131 The MIPS architecture manual says it is implementation-dependent whether the non-enabled interrupt will make wait to continue. > There are also a number of MIPS platform specific workarounds to implemen= t idle. > > I'd really appreciate some feedback on this and hopefully a correct solut= ion. :) > > > > Adrian > > Index: mips/machdep.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- mips/machdep.c =A0 =A0 =A0(revision 225610) > +++ mips/machdep.c =A0 =A0 =A0(working copy) > @@ -497,7 +497,16 @@ > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0critical_enter(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu_idleclock(); > =A0 =A0 =A0 =A0} > - =A0 =A0 =A0 __asm __volatile ("wait"); > + > + =A0 =A0 =A0 intr_disable(); > + =A0 =A0 =A0 if (sched_runnable()) { > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 intr_enable(); > + =A0 =A0 =A0 } else { > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* XXX this isn't atomic! */ > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 intr_enable(); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 __asm __volatile ("wait"); > + =A0 =A0 =A0 } > + > =A0 =A0 =A0 =A0if (!busy) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu_activeclock(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0critical_exit(); JC.