From owner-svn-src-stable-8@FreeBSD.ORG Tue Aug 18 20:25:02 2009 Return-Path: Delivered-To: svn-src-stable-8@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D12B0106568D; Tue, 18 Aug 2009 20:25:02 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id A34908FC3F; Tue, 18 Aug 2009 20:25:02 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n7IKP2mu027504; Tue, 18 Aug 2009 20:25:02 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n7IKP2Ep027502; Tue, 18 Aug 2009 20:25:02 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <200908182025.n7IKP2Ep027502@svn.freebsd.org> From: Pyun YongHyeon Date: Tue, 18 Aug 2009 20:25:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r196367 - in stable/8/sys: . amd64/include/xen cddl/contrib/opensolaris contrib/dev/acpica contrib/pf dev/mii dev/xen/xenpci X-BeenThere: svn-src-stable-8@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 8-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Aug 2009 20:25:02 -0000 Author: yongari Date: Tue Aug 18 20:25:02 2009 New Revision: 196367 URL: http://svn.freebsd.org/changeset/base/196367 Log: MFC r196366: Backout r193289. r193289 restored page select bits to previous value instead of blindly resetting it to 0. However, it seems page select bits of some 88E1116 PHY is initialized to invalid one such that restoring page select bits after programming broke MII register access. The correct solution would be reset page select bits to 0 in PHY attach stage but it would require more testing. Since we're in BETA stage such a change would be dangerous so just back it out. This change should fix nfe(4) breakage on NVIDIA MCP55. Reported by: Ryan Rogers < webmaster <> doghouserepair dot com > Sam Fourman Jr. < sfourman <> gmail dot com > Tested by: Ryan Rogers < webmaster <> doghouserepair dot com > Sam Fourman Jr. < sfourman <> gmail dot com > Approved by: re (kib) Modified: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/mii/e1000phy.c stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/mii/e1000phy.c ============================================================================== --- stable/8/sys/dev/mii/e1000phy.c Tue Aug 18 20:20:15 2009 (r196366) +++ stable/8/sys/dev/mii/e1000phy.c Tue Aug 18 20:25:02 2009 (r196367) @@ -240,13 +240,11 @@ e1000phy_reset(struct mii_softc *sc) if (esc->mii_model == MII_MODEL_MARVELL_E1116 || esc->mii_model == MII_MODEL_MARVELL_E1149) { - page = PHY_READ(sc, E1000_EADR); - /* Select page 2, MAC specific control register. */ PHY_WRITE(sc, E1000_EADR, 2); reg = PHY_READ(sc, E1000_SCR); reg |= E1000_SCR_RGMII_POWER_UP; PHY_WRITE(sc, E1000_SCR, reg); - PHY_WRITE(sc, E1000_EADR, page); + PHY_WRITE(sc, E1000_EADR, 0); } }