Date: Fri, 14 Jun 2002 10:46:23 +0100 From: tony@ubik.demon.co.uk To: "Sergey Lyubka" <devnull@uptsoft.com>, hackers@freebsd.org Subject: Re: locore.s quiestion Message-ID: <E17Inex-0008gZ-0U@anchor-post-30.mail.demon.net> In-Reply-To: <20020614115010.B20213@oasis.uptsoft.com>
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devnull@uptsoft.com wrote: > Hello, Hi > I am writing an article about FreeBSD's startup > and kernel init > (it is at http://oasis.uptsoft.com/~devnull/dh/boot.html > for whom it may be interesting) I get a "no route to host" error. > I am stucked at two lines in locore.s (IA 32 arch) > > /usr/src/sys/i386/i386/locore.s: > > pushl $begin /* jump to high virtualized address */ > ret > > /* now running relocated at KERNBASE where the system is linked to run */ > begin: > /* set up bootstrap stack */ > > My question is: > why this is done. My understanding was that the loader > loaded the kernel at high virtual address already, > so there's no need to jump. It does exactly what it says on the tin. (To quote a long running UK tv advert series.) This code runs in real mode. The code prior to this detects the cpu type, etc... then sets up the virtual/paged memory mapping tables, then immediately prior to the code you quote is this bit: /* Now enable paging */ movl R(IdlePTD), %eax movl %eax,%cr3 /* load ptd addr into mmu */ movl %cr0,%eax /* get control word */ orl $CR0_PE|CR0_PG,%eax /* enable paging */ movl %eax,%cr0 /* and let's page NOW! */ Which enables paged memory mode in the processor control register. However to actually start using paged memory Intel's CPU documentation requires a flush and reload of the instruction stream. The pushl & ret are a convenient way to do this, possibly recommended by Intel - I don't have the relevant documentation to hand. The result is that the instruction after 'begin:' is the first to be executed in paged mode. Cheers, Tony To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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