Date: Thu, 22 Oct 2015 08:02:27 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r289744 - head/sys/mips/atheros Message-ID: <201510220802.t9M82RBG000475@repo.freebsd.org>
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Author: adrian Date: Thu Oct 22 08:02:27 2015 New Revision: 289744 URL: https://svnweb.freebsd.org/changeset/base/289744 Log: arge: use 1-byte TX and RX alignment for AR9330/AR9331. This part seems to work bug-free with single byte TX/RX buffer alignment. This drops the CPU requirement to bridge 100mbit iperf from 100% CPU to ~ 50% CPU. Tested: * AP121 (AR9330) SoC, highly magic netbooted kernel + USB rootfs due to 4mb flash, 16mb RAM; doing bridging between arge0 and arge1. Notes: * Yes, I likely can also turn this on for the AR934x SoC family now. But since hardware design apparently follows similar branching strategies to software design, I'll go and make sure all the AR934x's that made it out into shipping products work before I flip it on. Modified: head/sys/mips/atheros/if_arge.c Modified: head/sys/mips/atheros/if_arge.c ============================================================================== --- head/sys/mips/atheros/if_arge.c Thu Oct 22 07:22:05 2015 (r289743) +++ head/sys/mips/atheros/if_arge.c Thu Oct 22 08:02:27 2015 (r289744) @@ -653,6 +653,8 @@ arge_attach(device_t dev) * Hardware workarounds. */ switch (ar71xx_soc) { + case AR71XX_SOC_AR9330: + case AR71XX_SOC_AR9331: case AR71XX_SOC_QCA9556: case AR71XX_SOC_QCA9558: /* Arbitrary alignment */
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